SU1529470A1 - Device for limiting clock pulses - Google Patents

Abstract

The invention relates to television. The purpose of the invention is to improve noise immunity by dynamically maintaining a given amplitude of clock pulses. The device contains an integrator 1, an adder 2, an amplitude limiter 3, a zeroing unit 4, a delay delay 5, a source 6 of direct current and an inverter 7. When applying intense harmonic interference, the period of which coincides with the period of the clock signal of the full television signal occurs a decrease in the constant component of these sync pulses. In order to restore the constant component of the clock pulses to a predetermined value, under the conditions of intense harmonic interference, the received full television signal is measured and limited in amplitude, and the tops of the clock pulses are also extracted from this full signal. To eliminate the undesirable phase delay of the trailing edges of the sync pulses during their correction, zeroing is performed. 1 il.

Description

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SP 1C

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The invention relates to television technology and can be used in cascades of cadre and line scanning of television systems.

The purpose of the invention is to improve noise immunity by dynamically maintaining a given amplitude of clock pulses.

The drawing shows the structural electrical circuit of the device for limiting clock pulses.

The device for limiting the clock pulses contains the integrator 1, the adder 2, the amplitude limiter 3, the zeroing block 4, the delay element 5, the DC source 6 and the inverter 7.

The integrator 1 contains an amplifier 8, a diode 9, a capacitor 10 and three P-13 resistors.

The zeroing unit 4 contains a key 14, to the input 15 of which a voltage reference signal is given.

Inverter 7 contains an amplifier 16 and two resistors 17 and 18.

The device works as follows.

In the absence of interference, the received full television signal, for example, of positive polarity, passes through adder 2 and amplitude limiter 3 without any correction. Integrator 1 performs the drive function. In this mode, the capacitor 10 is bridged by a diode 9 on a positive signal. Turning on key 14 does not affect its operation.

When imposing an intense harmonic interference, the period of which follows the sync pulses of the full television signal, the constant component of these sync pulses decreases to the value A. By decreasing the constant component A. 1, the conditions of the time selection and synchronization devices deteriorate line and frame sweeps. Failures in the synchronization operation occur as the power of the sync pulses decreases when the square of their vertices is violated.

To restore the constant clock component to the value of L under the conditions of intense harmonic interference, the received full television signal is measured and limited in amplitude, for example, using limiter 3, and the tops of the clock pulses are extracted from this full television signal.

At the moments when the received full television signal containing the harmonic interference, the limiting level A, is received, the limited part of the harmonic interference by the integrator 7 is integrated, which implements the accumulation operation of the limited part of the harmonic interference. Diode 9 does not have a shunt effect. The output signal, after inversion by amplifier 8, is summed by adder 2 with the full received television signal.

To eliminate the undesirable phase delay of the trailing edges of the sync pulses during their correction, block 4 is used for zeroing. For this purpose, the sync pulses are delayed in element 5 for the duration of the sync pulse. After the delay time has elapsed, the output signal of the delay element 5 switches on the key 14, which zeroed in integrator 1, connecting input 15 to the input of integrator 1.

Sourcebook 6 sets the level of limit A ,. The integrator 1 is implemented on an amplifier 8, in a negative feedback circuit of which a capacitor 10 and a diode 9 are connected in parallel. Resistors 11–13 determine the value of the transmission coefficient of integrator 1. Inverter 7, implemented on amplifier 16 and two resistors 17 and 18, provides the required polarity of the signal at the input of the adder 2.

Claims (1)

Apparatus of the invention for limiting a sync pulse generator comprising an amplitude limiter, a source of direct current and a series-connected integrator and an adder, characterized in that, in order to improve the noise immunity by dynamically maintaining a given amplitude of clock pulses, an integrator, a delay element and an nulling unit are introduced the input of which is connected through the delay element with the output of the amplitude limiter, the input of which is connected to the output of the adder, the second input of the adder Is input to the device and is connected to 51529470 the first input of the integrator, the second and direct current, and the zeroing unit, the third inputs of which are connected to the output of the integrator and connected to the input by the moves, respectively. , inverter source.