SU1520517A1 - Device for diagnosis of digital units - Google Patents

Abstract

The invention relates to automation and computing and can be used in devices for test diagnostics of digital nodes and blocks. The purpose of the invention is to increase speed. The device contains memory blocks 1-4, control unit 5, display unit 6, defect fixing unit 7, switching unit 8, control unit 9. Device diagnostics nodes can operate in four modes: switching, operability check, defect search, check or loop search. In the switching mode, the diagnostics object contacts are divided into input and output. In the health check mode, all diagnostic objects are divided into workable and inoperable. In the defect search mode, the defects are localized. In the scan or search mode in a cycle, it is possible to measure the parameters of the objects being diagnosed. A positive effect is determined by the independent operation of the diagnostic nodes. 10 il.

Description

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The invention relates to automation and computing, namely to devices for testing diagnostics of digital nodes and blocks.

The aim of the invention is to increase speed.

The device allows iero to be used for multi-point diagnostics of digital nodes as follows. The automated diagnostics system of digital nodes consists of a central post consisting of a control unit and memory blocks, and n diagnostics posts, each of which contains a switching node from a switching unit, a display node from a display unit, a defect fixing unit from a defect fixing unit.

The central post is connected to the diagnostics posts by which the switching test, checking test, defect search test and corresponding defect lists are supplied to the control nodes. The selection of the frequency of reading each type of information and launching the automated test is carried out on the main post. diagnostic systems. Operators at diagnostic stations - connect digital nodes, called “diagnostic objects (OD), to the control nodes and in these nodes set the operation mode. Post diagnostics can work in a couple of modes: switching, operability check, defect search, welding, or loop search. In the switching mode, the contacts of the OD are divided into input and output using a switching test. In the health check mode, all ODs are divided into workable and inoperable. In the mode of searching for defects in an inoperative PD, defects are found and eliminated. In the test or search mode in a cycle, the operator has the ability to measure the parameters of the OD with the help of instrumentation equipment. All of the diagnostics work independently of one another, so that all the PDs can be diagnosed at the same time.

1 shows a functional diagram of the device; 2 is a diagram of a control unit i in FIG. 3 is a diagram of a control unit; FIG. 4 is a diagram of an address generation unit; FIG. 5 is a diagram of a node for setting the mode of a control block;

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NINJ in FIG. 6 is a diagram of the synchronization unit of the control unit; FIG. 7 is a block diagram of setting the control node mode; on Fig - removal of the synchronization unit of the node control; Fig. 9 shows the algorithm of operation of the device; Fig. 10 shows the type of information necessary for diagnosing.

A device for diagnosing digital nodes (Fig. 1) contains a memory block 1-4, a control unit 5, an indication unit 6, a defect fixation unit 7, a switching unit 8, a control unit 9. In addition, FIG. 1 shows a diagnostic object 10.

The control unit 5 (Fig. 2) comprises an address generation unit 11, a mode setting unit 12, a synchronization unit 13, a decoder 14.

The control unit 9 (FIG. 3) contains a register, 15 switching, information register 16, switch 17, comparison unit 18, synchronization unit 19, operation mode setting unit 20.

The address generation unit 11 (Fig. 4) contains counters 21 and 22. Node 12 (Fig. 5). contains Start key 23, Stop key 24, group of 25 keys Frequency Code, delay element 26, master oscillator 27, frequency divider 28.

The node 13 synchronization (Fig. 6) contains the elements NOT. 29, 30, elements And 31, 32, elements 33 - 37 delay, the switch 38.

The mode setting unit 20 (FIG. 7) contains the Cycle 39 key, the Test 40 key, the Search 41 key, the HE elements 42, A3, the delay elements 44 and 45, the AND elements 46, 47, the OR element 48, the Commute key 49.

The synchronization unit 19 (FIG. 8) contains a switch 50, elements AND 51-53, elements OR 54, 55, a counter 56, a decoder 57, triggers 58 and 59, delay elements 60-64, a switch 65.

The memory unit 1 is for storing a defect search test. From the output of memory block 1, command information1D1 is output to the input of control unit 5, to the inputs of switching unit 8 test words from the defect search test.

The memory unit 2 is designed to store the verification test. From the output of the memory block 2, the command information is output to the input of the control block 5, to the inputs of the switch block 8

cations are test words from a test.

The memory unit 3 is designed to store a switching test coming from the output of the memory unit 3 to the inputs of the control nodes 9,

The memory block 4 is intended for storing lists of defects corresponding to the test words of the test of the defect and coming from the output of the memory block 4 to the inputs of the block 7 of defect defectization.

The control unit 5 organizes the storage of all the units of the device. From the output of the control unit 5, the address information for reading information from the blocks 1-4 of the memory is input to the input of the memory blocks 1–4, and the command information to the inputs of the control units 9.

The display unit 6 is intended for a display indication separately for each object. 10 message diagnostics. Good, Failed, Defect not found and lists of found defects.

The defect fixing unit 7 is intended for storing separately for each inoperative object the diagnosis of lists of found defects coming from the output of the defect fixing unit 7 to the display unit 6.

Switching unit 8 is designed to connect each node of the 9-control separately to memory block 1 or memory block 2. The checkout test or defect search tester does not arrive from the outputs of the switching unit 8. inputs of nodes 9 control.

The control unit 9 is designed to set the operation mode of the display unit 6, the defect fixing unit 7, the switching unit 8, the control unit 9 Conrol J of the contacts of the diagnostic object 10 into input and output; supplying test information to input contacts comparing responses from output contacts and reference responses. From the outputs of the control unit 9, the command information is outputted to the inputs of blocks 6-8, to the test information diagnostics object 10.

A device for diagnosing digital nodes is as follows.

On command from control unit 5 is set to its original state

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control unit 5 and control unit 9 control. Then, from within the control unit 5, from the memory unit 1, the defect finding test begins to read, from the memory unit 2, the verification test, from the memory unit 3, the switching test, and from memory unit 4, the lists of defects. The device is ready for operation. Further operation of the device is determined by the modes of operation at the control nodes 9. The control unit 9 can operate in four modes: switching, performance check, defect search, check or loop search.

In the switching mode by commands from control unit 5 and. From the control node 9 to the control node 9 from the memory block 3, a switching test is recorded, according to which the control node 9 performs the required separation of the external contacts of the diagnostic object 10 into input and output.

In the health check mode, on command from the control node 9, the switching unit 8 connects the output of the memory block 2 to the input of the control node 9. Then, at the command from control unit 5, the control unit 9 from memory unit 2 reads the first test word from the testing test and compares the response received from the diagnosis facility 10 with the expected reference response. There are two options for continuing the operation of the device.

If the compared reactions are not equal, then the control unit 9 finishes its work and upon a command from the control unit 9 in the indication unit of the id unit 6, corresponding to the diagnostic object under test 10, the display of the Nass- message is provided. right

If the reactions being compared are equal, the operation of the device is repeated on the next test word.

If the testing test has passed to the end, then the control unit 5 stops the operation of the control unit 9. Then, a command from the control unit 9 in the display unit 6 is provided with an indication of the message. Regularly, the diagnostic object 10 being checked is checked.

. In the defect-finding mode by command from node 9 of the control unit 8, commun0

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This module connects the output of memory block 1 to the input of node 9 of the control unit. Then, the command from the control unit 5 to the control unit 9 from the memory glint 1 reads the first test word from the defect search test and compares the result. from the facility 10 diagnosing the response with the expected reference response. There are two options for continuing the operation of the device. If the compared reactions are equal, then the node 9 Control finishes its work and enters a command whereby the defect fixing node of the defect fixing unit 7 corresponding to the given diagnostic object 10 records a list of found defects from memory block 4. Then, a command from the monitoring unit 9 in the display unit of the display unit 6 corresponding to this diagnostic object 10 provides an indication of the list of found defects coming from the defect fixing unit 7.

If the compared reactions are not equal, then the operation of the device is repeated in the next test word.

If the defect detection test has passed to the end, then the control unit 5 stops the operation of the control unit 9. Then, a command from the control unit 9 in the display unit 6 is provided and the indication of the message Defect not found. This means that the defect present in the object 10 of the diagnostics is not contained in the list of defects for which the defect search test is built. In the 3iTOM case, it is necessary to search for a defect in the test mode or cycle search using, for example, instrumentation, and from the search results, correct the list of defects and, as a result, change the defect search test stored in memory block 1. .

In the test or search mode in a cycle, the device operates as described, in the corresponding mode, without stopping until the device is taken out of the test mode or search in a cycle.

The control unit 5 operates as follows.

The operation of block 5 begins with the appearance at the output of node 12 of setting the frequency code frequency mode, which is

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It goes to synchronization node 13 and provides a choice of reading frequencies for the PT checking test, CT switching test, and TPD defect detection test. Then, in the code of the mode setting node 12, a single reset signal appears, which arrives at all the control nodes 9 and sets them to their initial state, enters the address generation node 11 and sets zero outputs of the checking test and СЧ2 test addresses on its outputs defects search. Then, a clock pulse appears at the output of node 12, which arrives at synchronization node 13 and causes the output of the SCTS signal to read the switching test, which goes to memory block 3 for reading the switching test, the signal of the SCTPT of the checking test, which together CQ1 goes to memory block 2 for reading the test word of the test test, signal. The SCTGSC of the defect search test, which, together with SC2, enters the memory block 1 for reading the TFD test word, the signal of the SCTS, reading the list of defects, which together with the SC2 enters the memory block 4 for reading the list of defects. After the time required for reading information from memory blocks 1-4, at the output of synchronization node 13, SCST, SCTP, SCTPD signals appear, which are sent to control nodes 9 as command information. The operation of the control unit 5 is repeated on the following TI.

If KPT is read — the end of the testing test or the QTFA — the end of the defect search test, then the operability test or defect search is completed. In this case, a single HIT or TFCA signal appears at the output of the decoder 14, which arrives at the synchronization node 13 and prohibits the generation of signals of the SCTPT, CTPTP arriving at the control nodes 9, and also goes to the control nodes 9 as command information.

The operation of the control unit 5 ends after the termination of the appearance of the clock control pulses at the output of the console 12.

Node 9 control works as follows.

In the control panel 20, the operation mode is set: switching.

performance check, search

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defects, checking or searching in a cycle,

In the switching mode, the single switching signal KM from the output of block 20 goes to the synchronization unit 19 and, together with the switching test SCCP signal, provides the output at the output of the synchronization block 19 of the single switching test write switching signal that goes to the switching register 15 and allows writing to switching register 15 from block 3 of the switching test memory.

In the health check mode, a single health check signal PR from the outputs of block 20 is supplied to switching unit 8 for connecting to register 16 information of output of memory block 2, as well as to synchronization block 19 and, together with the control signal, the end of the checking test from control block 5 prepares block 19 synchronization to work in the mode PR. Then, from the control unit 5 to the synchronization unit 19, the signal of the SCTPT reads the checking test, which causes the output of the synchronization unit 19 to cause the TESF signal to write the test word to the information register 16 and record the first test vehicle test word from the unit 2 memories in regis 16 information.

The test word consists of the TH of the test set coming from the output of the register 16 information through the switch 17 to the object 10 for diagnostics and the ER of the reference reaction coming from the output of the register 16 information through the switch 1 to the input of the object 18 of the comparison. The other input of the comparator unit 18 from the diagnostics object 10 through the switch 17 receives the signal OP of the response. Then, after the time required to set up the OP in the diagnostics object 10, the output of the synchronization unit 19 of the synchronization unit 19 results in the resolution-equalization signal. that comes to block 18 comparison and resolves the comparison of ER and OR. Two options are possible to continue the operation of the control node.

If the ER and OR are not equal, then the SRV comparison signal from the output of the comparison block 18 is absent and the block 19 is synchronized

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the control, as well as providing an indication signal to the display unit 6, the IISP signal is faulty, by which the message indication is provided in the display unit of the display unit 6 corresponding to the diagnostic object 10 to be diagnosed.

If the ER and OR are equal, then the SRV signals from the output of the comparator unit 18 are fed to the input of the synchronization unit 19 and the operation of the control unit 9 is repeated on the next vehicle.

If the checking test has passed to the end, then the synchro 19 end of the checking test is sent to the input of the synchronization unit 19 from the control unit 5, according to which the synchronization unit 19 terminates the operation of the monitoring unit 9, and also sends an ICP signal to the display unit 6 Rightly, the message indication is provided on the display unit of the display unit 6 corresponding to the diagnostics object 10 to be diagnosed.

In the defect detection mode, a single signal PD for detecting defects from the output of block 20 goes to switching block 8 for connecting to register 16 of information output of memory block 1, as well as to synchronization block 19 together with the CTC signal of the end of defect detection test from control block 5 and prepares the synchronization unit 19 for operation in PD mode. Then, from the control unit 5 to the synchronization unit 19, a CTPTP signal is received to read the defect finding test, which causes the output of the TORPTS signal at the output of the synchronization unit 19, which enters the information register 16 and records the first vehicle defect detection test from memory 1. in register 16 information. From the register 16 register, through the switch 17, the pump enters the TN to the object 10 of the diagnosis, as well as the ER to the input of the comparison unit 18. At the other input of the comparator unit 18 from the diagnostics object 10, the OP enters through the switch 17. Then, after the time required to establish the OP in the diagnostic object 10, the output of the synchronization unit 19 of the comparison resolution signal appears, which goes to the comparator unit 18 and resolves

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singing of ER and OR. There are two possible ways to continue the work of the node 9

If the ER and OR are equal, the SRV signals from the output of the comparator unit 18 are fed to the input of the synchronization unit 19, which terminates the control unit 9, and also issues a defect protection signal block on the defect fixing unit 7, through which the defect fixation unit 7, the fixation of defects, corresponding to this object 10 of diagnosis, is recorded by the AN from the block 4 of memory. Then, the defect indication ID signal from the synchronization unit 19 in the display unit of the display unit 6, corresponding to this diagnostic object 10, is provided with an indication of the SD coming from the defect fixing unit 7.

If the ER and OR are not equal, then the SRV signal from the output of the comparison circuit 18 is absent at the input of the synchronization unit 19 and the operation of the control unit 9 is reversed on the next vehicle.

If the defect-finding test has passed to the end, then the input of the QTFD of the end of the test, the search for defects, by which the synchronization unit 19 finishes the operation of the control unit 9, is sent to the input of the synchronization unit 19, and also gives the DNN- signal to the indication unit 6 defect. - not found, by which indication of cor- communication is provided in display unit 6 Defect is not found.

In the mode of checking or searching, the output of the control center appears at the output of the control panel 20 - a cycle and one of the PR, PD signals, which arrive at the synchronization unit 19 and ensures the operation of the control unit 9 as described, in the corresponding mode, without stopping up to the moment of termination on the left at the output of block 20 of the signal of the DD, i.e. until the output of node 9 of the control from the test mode or search in a cycle.

The address generation unit 11 operates in the following manner.

From node 12 of setting the mode to the input of node 11 of Forming an address, the CBP signal is sent — a reset, which resets the counters 21 and 22. The contents of the counters as addresses are sent to blocks 1, 2 and 4 of memory for reading the defect finding test, checking test and

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defect lists. Then, from the synchronization node 13 i, the signals + 1СЧ1, + 1СЧ2 are sent to the input of the address 1 1 1 address, whereby the counter content 21, 22 increases by one unit. The counter 21 counting coefficient is one more than the number of test words in the testing test. and the conversion factor of counter 22 is one more than the number of test words in the defect search test, so after reading the last test word and in the testing Test or in the defect search test, the reading of the test word automatically occurs.

The node 12 task mode works as follows.

On a group of 25 keys, the Frequency Code is set to an RC — a frequency code that arrives at the synchronization node 13 and sets the readout frequencies of the switching test, the verification test, and the defect search test. Then, a single signal from the output of the Start button 23 arrives as a CBR reset signal to the address generation unit 11 and to all control nodes 9 for resetting them, as well as after the time required for setting the address generation unit 11 and control node 9 to the initial state. state and determined by the element 26 of the delay, as a start signal to the master oscillator 27 and starts it. Clock pulses from the output of the master oscillator 27 and from the outputs of the frequency divider 28 are sent to the synchronization unit 13 to ensure its operation. A single signal from the output of the Stop Button 24 goes to the master oscillator 27 and stops it.

Node 13 synchronization works as follows.

From the node 12 setting the mode to the input of the node 13 synchronization receives the frequency code, according to which the switch 38 connects each input of the delay elements 35-37 to the selected TI input of clock pulses, i.e. The SQT frequencies of the switching test, the SCCT reading of the checking test, and the SXTPD of the defect finding test are specified. Then, the input of the synchronization node 13 from the mode setting node 12 is received by TIs, which cause the appearance of the SCTPD signals,

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SCTPT and SCTPT that go to memory blocks 1-3 for reading the information contained in them. After the time required to read information from memory blocks 1–3 and determined by delay elements 35–37, the outputs of delay elements 37 and elements 32 and 31 produce SSCT, CSTD, CSTDD signals, which are received by control units 9 as command information. Then, from the decoder 14 to the input of the synchronization node 13, the CPT signals of the end of the checking test or the DFD of the end of the defect search are received, which cause the output of the elements HE 30 and 29 of zero signals arriving at the AND elements 32 and 31 and prohibiting the generation of signals of the SSTP , because from the blocks 2, 1 of the memory, the service information of the KIT or KTPD is read, which is not necessary to be written to the control nodes 9.

The mode setting unit 20 operates as follows.

In the switching mode, a single switching signal KM from the output of the Switching button 49 is supplied to the synchronization unit 19 to generate a TFMS signal to enable the switching test recording.

In the health check mode, a single check signal PR from the output of the Check 40 key goes to switching unit 8 for connecting to output register 16 information of memory 2, to synchronization unit 19 to prepare it for operation in OL mode, and also through 46, OR 48 as a start request signal to synchronization unit 19 to prepare it for operation in PR mode. After the time required to set the synchronization unit 19 and determined by the delay element 44, a zero signal appears at the input of AND 46, which stops the pitch signal from the output of the OR 48 element to the synchronization unit 19.

In the defect detection mode, the single defect detection signal PD from the output of the Search 41 key arrives at the switching unit 8 for connecting to the output information register register 16 of the memory 1, to the synchronization unit 19 to prepare it for operation in the PD mode, as well as through the elements 47 OR 48 as UCS signal to synchronous node 19

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to prepare him for work in PD mode. After the time required to set the synchronization unit 19 and determined by the delay element 45, a zero signal appears at the input of the AND 47 element, which stops the supply of the UCS signal from the element output. OR 48 to block 19 synchronization.

In the scan or scan mode, a single signal of the CC from the Cycle 39 key output is an act to the synchronization node 19 to prepare it for operation in the CC mode. Then the operation of block 20 occurs as described, in the appropriate mode. The synchronization unit 19 operates as follows.

From the control unit 5, a reset signal CBR is received, which sets the trigger 38, the trigger 59 and the counter 56 to the zero state.

In the switching mode, block 20 receives the switching signal KM, which sets trigger one 58 to a single state. The output from trigger output 58 arrives at the input of element I 53 and allows the SCHT signal to pass through the switching test that passes through element And 53 to pass through it. the signal as a signal of the RCDCT for recording the switching test is fed to the switching register 15, and after the time required for the SCTS signal to pass through the element 53 and determined by the delay element 62, from the output of the delay element 62 Erez OR gate 54 sets the null state the trigger 58.

In the health check mode, block 20 receives a start-up PSK signal, which flushes counter 56 and trigger 59 through element OR 55. Then, from block 20, a health check signal PR arrives at the decoder 57 and causes a zero signal at the output of the decoder 57 to the inputs of switches 50 and 65 and connects the input of the CSTD to the input of the And 5 1 element, and the input of the KPT to the input of the And 52 element. At the same time, together with the zero signal TO, the defect was detected from the output of the delay element 61 and with the contents of the counter 56, not equal Two, at the output 6 of the decoder 57, a single signal appears, which through the delay element 60 enters the input

element I 52. Then, from the control unit i, the signal KPT of the end of the testing test is received, which through the switch 50 and element I 52 goes to the counter 56 and increases its content by one.

The single contents of the counter 56. arrives at the decoder 37 and together with the zero signal of the CC, the zero signal TO from the output of the delay element 61 and the single signal PR provides the output at the output 2 of the decoder 57 a single signal which is fed to the input of the element 51. Then block 5 of the control receives the signal SCIT, which passes through the switch 65 element And 51 and enters as a signal RZPTS to register 16 information. At the same time, after the time required to establish a response at the output of the object 10 of the diagnostics and determined by the delay element 63, and the time required to generate the NRV signal in the comparison unit 18 and determined by the delay element 64, the signal of the VPC goes through the elements 63 , 64 delays as a RZSZ signal to the input of the decoder 57. The further operation of the synchronization unit 19 is determined by the presence or absence of the SRV signal from the comparison circuit 18, therefore, we consider two options

If the SRV signal is not present, the zero signal of the SRV at the output of the single signal is set to one trigger 59. The unit from the trigger output 59 through the delay element 61, designed to reliably install the trigger 59, enters the TO signal 57 fc signal at the input - the defect is detected. A single TO signal causes the appearance at outputs S, Z of the decoder 57 zero signals that go to elements 51 and 52 and stop the operation of the synchronization unit 19, and also together with the single signal PR causes the appearance at output C of the decoder 57 of a single signal of the IISP, which goes to display unit 6 and causes an indication of the message Failed.

If the CPB signal is present, then a single TO signal at the output of the delay unit 61 is absent and the operation of the synchronization unit 19 is repeated on the next SCTP signal.

If the verification test has passed to the end, then the QPT signal from the control unit 5 through the switch 50, the element 52 also increases by one the contents of the counter 56, which becomes equal to two. Such a counter content causes the appearance at outputs o, 2 decoders 57 of zero signals, which arrive at elements And 51 and 52 and stop the operation of the synchronization unit 19; and also, together with the zero signal TO and the single signal PR, the appearance at output q of the decoder 57 a single ICP signal, which goes to the display unit 6 and causes an indication of the message OK.

In the defect-finding mode, from block 20, the UCS signal is received, which, through element OR 55, zeroed the counter 56 and trigger 59. Then, from block 20, the defect-finding PD signal arrives, which arrives at the decoder 57 and causes a single signal at the output of the decoder 57 which enters the inputs of switches 50 and 65 and connects the SCTPD input to the input of the And 5A element of the KTPD input to the input of the And 52 element, and also causes occurrences with the zero signal TO from the output of the delay element 61 and with the contents of the counter 56, not equal to two e S decoder 57 single signal, which is through the delay element 60 is fed to the input element And 52. Then, from the control unit 5 receives the signal KTPD end of the test of the search for defects, which through the switch 50 and the element And 52 enters the counter 56 and increases its content by one .

The single contents of the counter 56 are fed to the decoder 57 and together with the zero signal of the CC, the zero signal TO from the output of the delay element 61, the single signal PD provides the output at the output 0 of the decoder 57 of the single signal which enters the input of the element And 51. Then from block 5 the control receives a SCTPD signal that passes through the switch 65, element 51, and arrives as a signal of the RZPTS to the information register 16, through the time required to establish a response at the output of the diagnostic object 10 and determined by the element ntom 63 delay through the delay element 63 as the MFF signal comparing unit 18, and

time) the time required for the generation of the SRV signal in the block. 18 are compared and determined by delay element 64 through delay elements 63 and 64 as a RHSA signal to the input of the decoder 57. Further operation of synchronization unit 19 is determined by the presence or absence of an SRV signal from comparison unit 18, therefore, we consider two options.

If the SRV signal is present, then by single PD signals, the SRV decoder 57 provides the output O of a single signal that sets the trigger 59 to a unit. The unit from the trigger output 59 through the delay element 61 to reliably install the trigger 59 enters the input decoder 57 as a signal to - a defect is detected. A single signal TO causes the appearance of the outputs about, 2 decoders 57 zero signals that go to the elements And 51, 52 and stop the operation of the block 19 synchronization, as well as together with a single signal MSH causes the appearance of the output and the decoder 57 single signals: RZPSD in which the defectone is recorded in block 7 of the defect list, and the ID in which the list of defects in the display unit 6 is received from the defect fixing unit 7.

If the SRV signal is not present, then a single DU signal at the output of the delay unit 61 is absent and the operation of the synchronization unit 19 is repeated on the next signal SCTPD.

If the defect detection test has passed to the end, then the KTPD signal from the control unit 5 through the switchboard 50 50, the AND element 52 increases by one the contents of the counter 56, which becomes equal to two. Such content

the counter causes the appearance on BEJXOs of 0.2, the decoder 57 null signals that go to the elements And 51, 52 and stop the operation of the synchronization unit 19, and together with the zero signal TO and a single signal PD causes the appearance of the decoder g 57 of a single signal of the DAYS, which goes to the display unit 6 and generates an indication of the message. The defect is not found.

In the test mode or search from block 20 to the decoder 57 enters

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the signal of the CC of the cycle, which causes the appearance at the output and the decoder 57 of a single signal, arriving at the input of the And 51 element and ensuring the continuous operation of the synchronization unit 19. Further operation of the synchronization unit 19 is performed as described in the corresponding mode, without stopping until the appearance of the signal of the CC at the output of the unit 20.

Claims (1)

Invention Formula A device for diagnosing digital nodes, comprising a switching unit, a display unit, a first memory unit, a control unit, n control units, a defect fixing unit, the first groups of information inputs and control nodes are combined and connected to the group of codes of the first memory block, read input which is connected to the output of the control unit, n groups of outputs of the switching unit are connected respectively to the second groups of information inputs n control units, the groups of inputs and outputs of which are groups of inputs and outputs y units for connecting to the input-output groups of diagnosed digital nodes, the group of information inputs of the display unit is connected to the group of information outputs of the defect fixation block. The recording inputs of which are connected respectively to the defect recording outputs, the control nodes, and the groups of setting inputs of which are combined and connected to the first group of outputs of the control unit, wherein the control unit contains a decoder, an address generation unit and a synchronization node, with the first input condition group of the control unit neither is coupled with a first group of inputs of the decoder, a group of outputs of which is connected with. the first group of inputs for setting the synchronization node mode, the first group of outputs of which is connected to the group of information inputs of the address generation node, the first group of outputs of which and the first output of the synchronization node are the second group of outputs of the control unit, the third group of outputs of which is connected to the second group of outputs of the address generation node and. with the second exit node synchronization, the second group of outputs of which forms the first group of outputs of the control unit, where the control node carries the switching register, the information register, the switch, the comparison block, the first group of information inputs of the switch is connected to the output group of the switching register, the group of inputs of which is the node control, the second group of information rods of which is connected to the group of inputs of the information register, the group of outputs of which is connected to the second group of information inputs of the switch, the first group of outputs of which is connected to the first group of inputs of the comparison unit, the second group of inputs of which is connected to the second group of outputs of the switch, the group of inputs-outputs of which is a group of inputs-outputs of the control node, characterized by speed, the second, third and fourth memory blocks are inserted into the device, with n groups of permitting inputs of the display unit connected to the output result control groups respectively Which are connected respectively with n groups of control inputs of the switching unit, the first group of information inputs of which are combined with the first group of inputs of the conditions of the control unit and connected to the output group of the second memory block, the group of address inputs of which are connected with the second group of outputs of the control unit, third group The pa of outputs of which is connected to the group of address inputs of the third-block of the memory block, the group of outputs of which is connected to the second group of informational inputs of the switching unit and to the second group of inputs of control unit, fourth group of outputs 0 five 0 five 0 five 0 five which is connected to the address input group of the fourth memory unit, the output group of which is connected to n groups of information inputs of the defect fixation unit, the operation setting node is entered into the control unit, the second input unit group of the control unit is connected to the second group of decoder inputs, the output group of which forms the first group of outputs of the control unit; the installation input of the address shaping unit is connected to the first group of outputs of the control unit and the installation output of the unit for setting the operation mode of the block control, the output group of the operation mode setting node of which is connected to the clock input group of the synchronization node, the third output of which is the output of the control unit, the second group of outputs of the address generation node and the fourth output of the synchronization node form the fourth group of outputs of the control unit, and the control unit is entered sync- and; ii and the unit for setting the operation mode, the enable inputs for recording the switching registers and information are connected respectively to the first and second outputs of the synchronization block, the input group Setpoint Assignments - the mode of which is a group of control set mode inputs, the output mode group of which is connected to the first group of outputs of the control node set operating mode unit, the second group of outputs of the operation mode block of which is connected to the second group of inputs of the synchronization unit mode set, the third output of which is connected to the comparison input of the comparison unit, the comparison output of which is connected to the trigger input of the synchronization unit, the fourth output and the output group of which are connected respectively with the output and the group of outputs of the result of the control of the control node. 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