SU1510104A1 - Cycle clocking device - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to reduce the time taken to synchronize. In the frame alignment device, the input digital signal containing sync groups is fed to register 1. Next, sync groups are detected by the decoder 2. It forms a single pulse at the synchronism position, which goes to elements 3, 11, and 16 and the inhibit unit 5. Pulses from the generator unit 18 also arrive at the element And 3 and the prohibition block 5. The coincidence of the pulses at the inputs of the element And 3 indicates the presence of synchronism and the element And 3 forms a single impulse. It enters through the element OR 4 to the drive 6, which drops its counter, and also overturns the RS flip-flop 15. The latter opens the AND 16 element and the pulses from the decoder 2 from now on through the element 16 and the OR element 12 drops the drive 13. The process continues until the frame alignment is disturbed. Next, the process of searching for synchronism is carried out, after which the device enters the mode of holding synchronism and waiting for its possible loss. 2 Il.

Description

SP

31510104

The invention relates to the field of telecommunications and can be used in digital transmission systems to provide frame synchronization.

The purpose of the invention is to reduce the time taken to synchronize.

Figure 1 shows a structural electrical circuit diagram of a frame alignment device; figure 2 - time-Q skalsansi. After a break in synchronism at the time of tuc (Fig. 2),

25

Signal diagrams of signals explaining his work.

The frame synchronization device contains a shift register 1, a decoder 2 sync words, a second IZ element, the first element OR 4, a prohibition block 5, an accumulator 6 at synchronization, the first large-scale voltage divider 7, the adder 8, the threshold block 9, the first element And 10, the third element 20 and 11, the second element OR 12, the accumulator 13 on the synchronization input, the second large-scale voltage divider 14, the RS flip-flop 15, the fourth And 16 element, the frequency divider 17 and the generator unit 18.

The device works as follows.

The information code of the frame alignment device receives a digital signal containing sync groups that follow with a constant period. Synchro groups are detected by a decoder 2, at the output of which a single pulse is formed at the synchronism position.

In the steady state cyclic synchronism is installed and the generating unit 18 and the divider 17 operate synchronously with the generating equipment of the transmitting side. In this mode, the generator unit 18 and the divider 17 produce single pulses at the position of frame alignment with the period corresponding to the frame frequency. j

The pulses from the first output of the generator unit 18 posts on the second element And 3 and block 5 of the ban. When the pulses coincide at the first and second inputs of the second element I 3, which indicates that synchronism is present, a single impulse is formed at the output of the latter, which through the first element OR 4 enters the installation input of the accumulator 6 and resets its counter to the zero state, as well as overturns the RS flip-flop 15. The last loop is the fourth element AND 16 and the pulses from the output of the decoder

35

40

50

55

NA

The sync group in the input signal is changed (hatched), and the generator unit 18 continues to generate pulses (with a period of the following TC) at the old synchronism points (not hatched). At the same time, two processes start simultaneously - filling the accumulator with 6 pulses from the generating unit 18 through the prohibition block 5 and filling the accumulator with 13 pulses of the new synchronization position from the decoder through the fourth element AND 16 and the second element OR 12. At the output of the adder 8, the signal appears , characterized by the filling value of accumulator 6 with weight K1 and the filling value of accumulator 12 with weight K2.

In this case, the weight characteristics (K1 and K2) of the output signals of the accumulators 6 and 13 are formed by the first and second scale dividers 7 and 14, respectively.

This signal is fed to the input of the threshold unit 9, which produces a single level, if at the same time the drive 6 has recorded the loss of the old synchronism and the drive 13 is fixed to find the new CONDITION of synchronism.

In the process of searching for synchronism, the pulses from the output of the decoder are also set through the fourth element AND 16 divider 17 to the state of new synchronism. After the triggering block 9 is triggered, the first element AND 10 and the new state of synchronism from the output of the divider are opened.

17Set the generator block

18 also into the synchronization state, after which the frame synchronization device goes into the synchronization hold mode and waits for its possible loss.

Claims (1)

Formula of the device The frame synchronization device containing the series-connected 2 from this moment through the fourth element AND 16 and the second element OR 12 is fed to the input of the accumulator 13, which by these pulses is reset to the zero state.  The described process continues until the frame alignment is not disturbed, for example, by skipping. After a break in synchronism at the time of tuc (Fig. 2), 25 20 ZO j 35 40 0 five NA The sync group in the input signal is changed (hatched), and the generator unit 18 continues to generate pulses (with a period of the following TC) at the old synchronism points (not hatched). At the same time, two processes start simultaneously - filling the accumulator with 6 pulses from the generating unit 18 through the prohibition block 5 and filling the accumulator with 13 pulses of the new synchronization position from the decoder through the fourth element AND 16 and the second element OR 12. At the output of the adder 8, the signal appears , characterized by the filling value of accumulator 6 with weight K1 and the filling value of accumulator 12 with weight K2. In this case, the weight characteristics (K1 and K2) of the output signals of the accumulators 6 and 13 are formed by the first and second scale dividers 7 and 14, respectively. This signal is fed to the input of the threshold unit 9, which produces a single level, if at the same time the drive 6 has recorded the loss of the old synchronism and the drive 13 is fixed to find the new CONDITION of synchronism. In the process of searching for synchronism, the pulses from the output of the decoder are also set through the fourth element AND 16 divider 17 to the state of new synchronism. After the triggering block 9 is triggered, the first element AND 10 and the new state of synchronism from the output of the divider are opened. 17Set the generator block 18 also into the synchronization state, after which the frame synchronization device goes into the synchronization hold mode and waits for its possible loss. The invention of the frame alignment device, containing sequentially connected shift register, sync code decoder, prohibition block, synchro-synchronous drive, first large-scale voltage divider, adder, threshold unit, first element, And, generator unit, second element, And the first OR element whose output is connected to the installation the frequency divider, the clock input and output of which are connected respectively to the clock input of the generator unit and the second input of the first element AND, the output of which is connected to the second input of the first OR element, the output of the synchrose decoder is connected to the second inputs of the second, the accumulator alarm output from the sync and the fourth element And, and vtonizma, sequentially connected frequency divider, the third element And, the second element OR, the drive at the entrance to synchronism and the second large-scale voltage divider, the output cat - 5 cerned is connected to the second input of the adder serially connected RS-trigger and a fourth AND gate, whose output is connected to the R-vkody RS-flip-flop, a second input of the second OR gate 20 and the mounting entry The inlet of the inhibit unit is connected to the output of the generator unit, the input of the shift register, the clock input and the second output of the generator block are respectively the information and clock inputs and the output of the device, characterized in that, in order to reduce the synchronization time, the output the second element And is connected to the S-input of the RS-flip-flop. the frequency divider, the clock input and output of which are connected respectively to the clock input of the generator unit and the second input of the first element AND, the output of which is connected to the second input of the first OR element, the output of the synchrose decoder is connected to the second inputs of the second, third and fourth elements And, and the second input the inhibition unit is connected to the output of the generator unit, and the input of the shift register, the clock input and the second output of the generator block are respectively the information and clock inputs and the output of the mouth An operation, characterized in that, in order to shorten the time to synchronization, the output of the second element AND is connected to the S-input of the RS flip-flop.