SU1506482A1 - Matrix storage for on-line memory - Google Patents

Abstract

The invention relates to microelectronics and is intended for use in digital devices. The aim of the invention is to reduce power consumption. This goal is achieved due to the fact that in the matrix accumulator there are 2 p-type epitaxial layer on the surface of the epitaxial layer between the 3 N ⁺ -type regions and the second lateral surfaces of the 12 grooves 13 p ⁺ -type regions are formed, with the semiconductor substrate 1 and the first semiconductor layers 7 is made of p ⁺ material of the conductivity type, and the second semiconductor layers 9 are made of N material of the conductivity type. 4 il.

Description

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The invention relates to microelectronics and is intended for use in digital devices.

The purpose of the invention is to reduce power consumption.

FIG. 1 shows a matrix drive, a cross section of the structure, in the row direction; in fig. 2 shows section A-A in FIG. one; in fig. 3 shows a section BB in FIG. one; in fig. And - the equivalent circuit of the storage element of the matrix drive.

The matrix storage device contains a semiconductor, for example, silicon substrate of 1 p-type and epitaxial layer 2 of p-type, the surface of which contains 3 p-type regions in the column. In the epaxial layer 2, grooves with a depth not less than the thickness of layer 2 are made, the first side surfaces 4 of which are granted with areas 3. On the surfaces of the grooves and epitaxial layer 2 are applied successively the first layers 5 of the dielectric and metal electrodes 6, which are the screws: . Between the metal electrodes 1 6 and the first side surface 4 of each groove there are seven semi-conductive semiconductor layers 1 p-1: a, separated from the metal electrodes 6 by the second layers 8

0

five

(part of the epitaxial layer) and the first semiconductor layer 7 form a MIS transistor with an induced n-type channel. Layers 7, 9, 3, and 6 form the source, channel, drain, and gate of the second MOS transistor with an integrated n-type channel, respectively. A p-type layer 13 prevents the occurrence of a parasitic connection between the n-area 3 and the substrate 1 along the surface of the substrate and the second side surface 12 of the groove.

Thus, the storage element has an equivalent circuit (Fig. 4). The diagram shows: 14 is a storage capacitor formed by layers 6, 8, 7; 15 - storage capacitor formed by layers 7, 5, 2, 1; 16 is a row bus, 17 is a column bus, 18 is an MIS transistor with an integrated n-type channel formed by layers 7, 9, Zibi designed for recording information, 19 is an MIS transistor 6 with an induced n-type channel, formed by layers 1, 2, 3, 7 and intended for combining the state.

The T5 mode of recording on bus 17 of the column is applied either to the low voltage of the shovel O (U - 0) or to the positive voltage of the logical 1 (and), and to the bus 16 of the selected row - positive or null 0

0

I1sh). Beside the surface of the epitaxial layer 2 and the metal, the narrow electrodes 6 are located 5 second semiconductors of a dielectric insulated from them by layers 5 (iianpn {ep, silicon dioxide);

module of the cut-off voltage of the transistor 18. On the non-selected immax rows, the voltage is negative. In the selected storage element, the transonic layers 9 are n-type, forming an omnibus 40, 18 are also unlocked in the storage

node C (Fig. 4) is set to voltage and or and. At the end of the recording and during the transition to the storage mode, the 16 lines in the tsgin are discontinuously usable by 3-type regions and the second lateral 45-negative surfaces of the 12 grooves are formed by 14 p-type regions.

The drive works as follows.

contacts 10 with the first semiconductor layers 7 and ohmic contacts 11 with 3 n -type regions. At the surface of the epitaxial layer between

and

AT

, p about point C (fig about 4), the voltage becomes equal to U. - (U ,, an

) C, / (C, + 0.5) in the case of storage of logical O or He, U - (and,., An- and ,,, p) C, / (C, + C, j) in the case of storage of logical 1, where Ci5 of capacitance of capacitors 14 and 15. Transistor 18 is locked, for which it is enough -Uv.xp + Uco sec. Transistor 19 is also closed, for this you need Uc then then horn voltage When combined

The substrate and the epitaxial layer are connected to the zero tire. The information in the storage element is stored as voltage on the storage capacitors formed by layers 6, 7, 8 and 7, 5, 2, 1, respectively. Areas 1 and 3 are of the n-type in each storage element together with the area located between them p-type

node C (Fig. 4) is set to voltage and or and. At the end of the recording and during the transition to the storage mode, on the 16 line string, the negative voltage is abruptly jumped.

and

AT

, p about point C (fig about 4), the voltage becomes equal to U. - (U ,, an

) C, / (C, + 0.5) in the case of storage of logical O or He, U - (and,., An- and ,,, p) C, / (C, + C, j) in the case of storage of logical 1, where Ci5 capacitance of capacitors 14 and 15. Transistor 18 is locked, for which it is enough –Uv.xp + Uco sec.

On 17-column cores, a positive voltage is pre-set (for example, U), which, at the end of the installation pulse, is maintained by the bus capacitance. Then, the voltage on the bus 16 of the selected line is increased to the value of the intermediate mezzot-i ,, p and, for example, to U and,, o1p-0.5 (and, „- - and, xr). As a result, at point C, the voltage becomes paBHbiM

and, - (and

with

x.eap UX.CM) CH / ((4 S

)

or

Ue, and - (U,., O, o- and,. С,) С „/ (С

U C, P;

In this case, the transistor 18 remains closed if the condition -Uj cc + UCQ Ug, is fulfilled. . Transistor 19 in the case of connecting the logical O should be closed (11 and "(, p), then the voltage on the bus 17 of the column remains unchanged. When reading the logical 1 and i" op, the transistor 19 is unlocked and the voltage on the bus 17 decreases, which perceived by the amplifier connected to the bus.

Claims (1)

Invention Formula A matrix storage device for a random access memory, containing a semiconductor substrate, with a p-type epitaxial layer located on it, in the near-surface layer of which there are areas 6 3 10 ; p-types forming column tires of the matrix accumulator, grooves are made in the p-type epitaxial layer, the depth of which overlaps the thickness of the p-type epitaxial layer, the first lateral surfaces of the P-grooves adjoin n-type areas on the surfaces of the grooves and the epitaxial layer r-gi 10 pas are applied successively the first layers of the dielectric and metal the electrodes that form the tires of the rows of the matrix accumulator between the metal electrodes and the first side 15, the surface of each groove contains the first semiconductor layers, separated from the metal electrodes by the second dielectric layers, between the surface of the epitaxial layer 20 p-type and metal electrodes are located isolated from them second semiconductor layers, forming contacts with the first semiconductor layers, which differs 25 with the fact that, with the power consumption reduction circuit, in the p-type epitaxial layer surface between mi p-type and repeat side surfaces-i The 30 tons of grooves are formed of p-type regions, the semiconductor substrate and the first semiconductor layers are made of an n-type conductivity material, and the second semiconductor layers are made of an n-type conductivity material. A-A B 10 9 ig.2 G4: f  one fie.Z 18 17 rt fieL