SU1501282A1 - Series to parallel code converter - Google Patents

Abstract

The invention relates to automation and computing and can be used to convert binary codes. The aim of the invention is to improve the noise immunity of the converter. The converter contains a shift register 1, triggers 2.3, elements NOT 4.5 and element IS-NOT 6 1 sludge.

Description

AI

J

5 К С

one

(L

SI

Launcher

Mode

V) s

g

3150

The invention relates to automation and hardware technology and can be used to convert binary codes.

The aim of the invention is to improve the noise immunity of the converter.

The drawing shows a diagram of the Converter.

The converter contains the shift register 1, triggers 2 and 3, the elements are NOT 4.5 and the element is NOT-6,

The Converter operates as follows.

Before the exchange begins, a signal is supplied to the converter via a setup input. A control word flag (CCP) is given, which reset the shift register 1, the triggers 2 and 3 modes. Further along the synchronous input are supplied the sync pulses (SI) and on the information input - information pulses (AI).

If a high level signal is set at the mode input, then a high level also appears at the output of trigger 3, which allows the SI to pass without shifting. At the same time, on the leading edge of the SI, information is recorded in register 1 shift a, and on SI decay, the trigger 2 is set to zero. Thus, the exchange mode used in the prototype is realized. A precondition is that the signals on the information input and D- the input of the shift register 1 must be filed before the SI for the synchronous inputs of trigger 2 and register 1,

In the case of a low level at the mode input in the initial state, at the output of the trigger 3 there is also a low level. Thus, the passage of the first SI to the output of the element AND-NOT 6 is blocked. Trigger 3 is driven by the decay of the inverted first clock pulse, allowing the SI to pass through the clock inputs of trigger 2 and register 1.

In shift register 1, information is recorded on the leading edge from the second SI. By this time, exit1282

ten

five

20

25

thirty

35

40

45

50

de flip-flop 2, which means that the processes at the input of pei-ister 1 shift are of steady state and the information is recorded (, the function is reliable. By the inversion of the inverted SI, trigger 2 of the record is reset.

Thus, the information pulse of the transmitted codogram can decay relative to the gating clock for a time that does not exceed the SI repetition period in the word, due to the shift between the sprinkling sync and CI readings per pulse, which increases the accuracy of the codogram reading.

Claims (1)

Invention Formula The serial to code converter in parallel, containing the first trigger, the output of which is connected to the D input of the shift register, and the first element NOT, the D input of the first trigger is connected to the low logic level bus, and the S and R inputs of the first trigger are respectively, the information and installation inputs of the converter, characterized in that, in order to increase the noise immunity of the converter, a high logic level bus, a second trigger, a second element NOT and an NAND element, the output of which is connected to the C-in input, are entered into it home nepBoi o trigger and through the first- Bbtfi element NOT - with the C-input of the shift register, the output of the second element is NOT connected to the C-input of the second trigger, the output of which is connected to the first input of the element AND-NOT, the second input of which is combined with the input of the second element NOT and is the synchronous input of the converter, the R-inputs of the shift register and the second trigger are combined and connected to the converter's input, the S-input of the second trigger is an input of the converter mode, D-input: the second trigger is connected to the high-level bus, outputs the shift register bits are the output of the converter.