SU1499521A1 - Switching device - Google Patents

Abstract

The invention relates to the field of automation and can be used in pulse distributors, counters, switches and shift registers. The purpose of the invention is to increase the reliability of work. The switching device contains switching cells 5, power buses 1, 2, power control switch 3. Each switching cell 5 contains an electromagnetic relay, which through its closing contacts 9 and the first diode 10 is blocked in operation. The second diode 11, the storage capacitor 12 and the transistor switch 13 generate a delay pulse of the next switching cell 5. To control the electrical bias of the transistor switches, a resistive voltage divider 4 connected to the power bus 1.2 via the switch 3 is used. 1 Il.

Description

3149

The invention relates to automation and can be used in pulse distributors, counters, switches and shift registers.

The purpose of the invention is to increase reliability.

The drawing shows an electrical schematic diagram of a switching device.

The switching device contains 1 and 2 power buses, a power control key 3, a resistive divider 4 bias voltage and serially connected cells 5 with inputs 6 and outputs 7 each.

The upper shoulder of the resistive divider 4 is connected to the power bus 1, the lower shoulder forms the first control bus and is connected via key 3 to the power bus 2, and the retraction of the resistive divider 4 forms the second control pin,

Each cell 5 contains an electromagnetic relay 8, the winding of which is connected to the power supply bus 1 by the first and the second output to cell 6 input 5 and through the closing contacts 9 of the electromagnetic relay 8 to the anodes of the first 10 and second 11 diodes. The cathode of the first diode 10 is connected to the first control bus, and the cathode of the second diode 11 is connected via a storage capacitor 12 to the power supply bus 2 and directly to the input of the transistor switch 13, the common output (emitter) of which is connected to the second control bus. exit 7 cells 5.

Switching device operates as follows.

If there is no recording, the electromagnetic relay 8 is in the de-energized state, and the storage capacitors 12, through the reverse resistance of the junction, the base-collector of the transistor switch 13 are charged to a voltage corresponding to the logical O and the bias determined by the voltage 4.

Recorded information corresponding to the code of any two-digit combinations is entered into the device by applying recording pulses corresponding to logical 1 to the inputs 6 of cells 5 in the absence of clock pulses, i.e. when the transistor switch 3 is in the conducting state.

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When writing a logical 1, the electromagnetic relay 8 goes into the excited state and blocks itself through the contacts 9, the first diode 10 and the key 3 onto the power bus 2.

The storage capacitors 12 remain charged to the logic level O, since the circuit of their charge from the side of the electromagnetic relay 8 of their cell is shunted by the key 3 and the first diode 10.

In the absence of clock pulses, this state can be maintained indefinitely.

With the arrival of the clock pulse, the key 3 goes into a non-conducting state, disconnecting the resistive divider 4, the first and second control buses from the power bus 2, de-energizing the power supply circuit of the windings of the excited relays 8 through the contacts 9 and the first diodes 10 from the second control bus, expanding the bypass circuit of the capacitors 12 through the first diodes 10,

The 12-cell storage capacitors, the electromagnetic relays 8 of which were in the excited state, begin to be charged along the power bus 1 circuit — the winding of the electromagnetic relay 8 — contacts 9 — the second diode 11 — the memory capacitor 12 — power bus 2. In this case, the diodes 10 1 prevent charging the storage capacitors of 12 other cells via the second control bus. Electromagnetic relays 8 remain in an excited state until the charge current of storage capacitors 12 reaches a value equal to the release current of the electromagnetic relay 8 of this cell 5. After releasing the electro-magnetic relay 8, the storage capacitors 12 remain charged to voltage corresponding to the logic level 1, since the transistor switch 13 is closed by the positive voltage of the power source supplied to its emitter via the first control bus and the upper (high-resistance) shoulder of the resistive divider 4 from the power supply bus 1, and the discharge of the storage capacitors 12 of the excited cells through the storage capacitors 12 of the other cells are prevented by the first diodes 10.

Along the trailing edge of the clock pulse, key 3 returns to its conducting state, lowering the potential

emitters of keys 13 up to logic level O and connecting a second control bus to power supply bus 2 common to all capacitors 12.

In cells 5, whose storage capacitors 12 were charged to a logic level 1, the positive potential of charged storage capacitors 12 is applied to the base-to-emitter junction. The transistor switch 13 opens, and the storage capacitor 12 starts discharging through the base-emitter transition and the lower (low-impedance) shoulder of the resistive divider 4. In this case, the coil of the electromagnetic relay 8 of the next cell 5 through the collector-emitter junction of the open transistor switch 13, the second control bus and the key 3 is connected to the power bus 2. Electromagnetic relay 8 is activated and self-blocked as described above. The collector of the transistor switch 13 is at a potential equal to the voltage drop in the first diode 10 and the switch 3. The transistor switch 13 closes, but the storage capacitor 12 continues to discharge through the base-emitter junction to a voltage corresponding to the logic level O, defined displaced from the lower (low-impedance) shoulder of the resistive divider 4.

After discharge of the storage capacitor 12, the circuit is ready to receive the next clock pulse.

Instead of a bipolar transistor Anizer B, a p-channel or a thyristor can be used as a key 13.

New connections of the electromagnetic relay 8, the transistor switch 13, the resistive divider 4 and the key 3 make it possible to more fully use the power supply voltage and the voltage of the charged storage capacitor 12, to reduce the power loss and the transient time during charging and discharging storage capacitors 12 , reduce the requirements for the power source and the elements used (permissible voltage values, the capacitance of the storage capacitors 12, the resistance value of the divider 4 resistors, etc.), which increases by ezhnost device in operation, its efficiency and rapidity the action allows to considerably simplify and konstruk1schyu circuit devices, reducing the number of contacts used and cell relay control circuits, reducing the device dimensions

Claims (1)

Invention Formula 20Switching device containing a power control key, a resistive bias voltage divider and serially connected memory cells, each of which is from an electromagnetic relay with a closing contact, in which the first winding terminal is connected to the bus Plus power supply, a storage capacitor, a transistor switch and 30 two diodes, distinguished by the fact that, in order to increase reliability, the first voltage divider from 1 st 11 is connected to the bus plus a lithium, the second output to the first control bus and through the power control key to the bus minus power, and the drain from the second the control bus, in each memory cell the second terminal of the winding of the electromagnetic Q relay is connected to the input bus of the cell and through the closing contact with the anodes of the first and second diodes, the cathode of the first diode is connected to the first control bus, the cathode of the second dd diode - with the input of a transistor switch and through a storage capacitor with a bus Minus power, the common output of the transistor switch is connected to the second control bus, and the output output is connected to the input of the following cell 50 mi ti