SU1497738A1 - Switching element using mis-transistors - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing devices as a logical or switching element. The aim of the invention is to enhance the functionality of the device by allowing two functions to be performed, both NOT and NAND, using both constant and pulsed or variable power sources or signals. The goal is achieved by connecting the signal source through the input resistor 1 to the substrate of one of the MOS transistor 2, which is connected in series with the second MOS transistor 3. Moreover, the cell is powered through the PN-transitions substrate-drain and the substrate-source of the first MOS transistor 2 The capacitors 4 and 5 serve as accumulative storage elements from which output signals are taken. 1 il.

Description

WITH

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H uirii) (TCHnc refers to iirn t rhinki impulse and can be used for computing and calculating T (jii) oti techniques and as a logical or switching olemeite.

The purpose of the “Justification” is the dissolution of the 11th 11th century and the 1 st capabilities of the key element through the implementation of two logical and commutation functions from two iiepeMQHiH.tx when using a single, continuous, or impulse source of nitrous, to gain control patterns and to get into the hands of 10-day control source, and to get into the hands of the 10-minute source of the nitrous source of the nitrous source of the nitrous source of the nitrate source. a resistor to the substrate of one of the MD11 transistors and i using the second condensate as a storage

In the drawing there is a schematic diagram of the key element on the MDG1 transistors e induced cat {a-lom n-tnpa,

The key element contains a resistor 1, the first 2 and the second 3.transistors, the first A and the second 5 are connectors to the gates of transistors 2 and 3 are connected to the first 6 and second 7 input terminals of the device. Transistors are connected in series, drain and i

the source of the first of them is connected to the alternate 30. It may not be

You, however, capacitors k and 3, through resistor 1 and np l immedicable pnp transitions substrate – drain and bend: 1g — the source of the transistor 2 transmits 2 — until the voltage of the signal bus is polarity.P.

When applying to the second input terminal 7 a single signal ko} 1 capacitor

5 through the second transistor 3 is discharged to the potential of the RPB; bus 10 to it. When the second input terminal 7 is cleared, the second capacitor 5 is again charged to the unit level. Thus, o & panoMj the second output 9 of the device fulfills the function of the logical inverter,

Ilpvi supply to both input terminals

6 and 7 single signals of the spacing device are discharged and a low level is set at the outputs 8 and 9;

When applying a constant supply voltage, the resistor J provides a predetermined voltage level at the outputs of the device. At HMnynbCHOh power supply on the sigpal bus 11 and with appropriate synchronization of the input signals, resistor 1 can

8 and the second 9, respectively, the output of the device, Me with the outputs 8 and 9 on the one hand and the common pshnoy 10 with the other included the first 4 and second 5 capacitors. The source of the second Tpai - resistor 3 is also connected to the common bus 10 "Signal bus 11 through a resistor 1 is connected to the substrate of the first transistor 2.,

The key element works as follows:

CIM il6jJ, 3OMo

Signal voltage 11 relative to common iiiHHbj 10 is supplied with positive polarity voltage or alternating voltage. The signal source can be either a constant source or a non-simultaneous voltage source or such a voltage source. as well as a pulse or harmonic signal generator, as well as a digital or analog element,

Capacitors 4 and 5 perform the function of a storage element that accumulates the charge of the positive field of the risk factor.

In the absence of positive signals at the input terminals 6 and 7 of the MOS transistors 2 and 3 on the gates closed

also at small (less than 0, / –0.8 V) voltage supply amplitudes. The role of the resistor 1 in this case will be ..., the full resistance of the pn j transition itself is about i

When a low level signal is applied to the first input terminal 6 regardless of the presence or absence of a single signal at the second input terminal 7, the first transistor 2 is closed and the voltage level is kept high at the first output 8. Thus, the key element at its first output 8 implements a logic the NAND function of two variables. At the same time, this element can be used as a digital or analog switching element, with control signals being fed to the input terminals 6 and 7, and to the signal bus 11 to mmutiruemsh signal which is removed from the outputs 8 and 9 of the device. Thus, the device implements the function of the distributor on the channel core, which works according to the logic NOT or AND NOT through both inputs.

When using an alternating signal source device to 51D977386

It performs the function efficiently, is connected to the input signals, mothers, and the free drain and source of the same

transistors are connected to a corresponding logical function to the first output of the device and to the key element on the comparison bus, between which a new capacitor is connected to the conventional logical element, and the first output of the second is NOT the capacitor is connected to the point of temporary performance of the function as a serial connection of the transis-AND-NOT and of the inverter, moreover, independent of the tori, characterized in that, in order to extend the functional input signaling capabilities, a resistor is inserted in the device, connected between the sig formula of the invention and the substrate

15 transistors, the first one of the second

The key element on the MIS transistor-capacitor is additionally connected pax, containing two transistors and two to the second output of the device, and the second-capacitor, transistor gates, swarm output of the same capacitor connected to each other recently to the common bus.

Claims (1)

The claims 15 Key element on MOS transistors, containing two transistors and two capacitors, transistor gates that are interconnected in series, connected to the input terminals, and the free drain and source of the same transistors are connected respectively to the first output of the device and to a current bus, between which the first capacitor is connected, and the first output of the second capacitor is connected to the serial connection point of transistors, characterized in that, in order to expand the functionality, a resistor is inserted between the signal bus and the substrate of the first transistor, the first terminal of the second capacitor is additionally connected to the second output of the device, and the second terminal of the same capacitor is connected to the common bus.