SU1488799A1 - Unit for organization of access to resorces - Google Patents

Description

The invention relates to computing and can be used for queuing for various resources in multiprogramming and multiprocessor computing systems. The purpose of the invention is the expansion of the functionality of the device due to the simultaneous formation of queues to heterogeneous resources. The device contains a request register, a group of requests type registers, a resource readiness register, a register of receivers type registers, a group of queue generation units, a clock generator, two delay elements, two triggers, four AND elements, three OR elements, two AND, η element groups groups for K elements (K is the number of resources, η is the number of applications), a group of subscriber selection nodes, a buffer register of applications. The device can operate in the modes of simultaneous queuing to different types of resources, ’shifting the queues for each resource or queuing for occupied different types of resources and queuing the shift for free. Queuing is ensured by having a queuing node for each resource with a subscriber selection node of the same type. 2 Il.

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The invention relates to computing and can be used to form a queue for various resources in multiprogramming and multiprocessor computing systems.

The purpose of the invention is the expansion of the functionality of the device due to the simultaneous formation of queues to different types of resources.

Figure 1 shows the block diagram of the device; figure 2 - block diagram of the node forming the queue.

The device (Figure 1) contains the register 1 applications, the buffer register 2 applications, the element OR 3, the register 4 resource readiness, the group of elements And 5, the elements And 6 and 7, the elements OR 8 and 9, the triggers 10 and 11, the generator 12 clock pulses, delay element 13, elements 14 and 15, delay element 16, η-groups for elements 17, element group 18, subscriber selection node 19,

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each of which includes in its composition a group of comparison circuits 20, a group of elements And 21, a group of elements And 22 and an encoder 23, registers 24 of the application type, a group of nodes 25 forming a queue, groups of η elements And 26, a group of registers 27 of the type of resource, inputs 28 applications of the device, inputs 29 of the type of applications of the device, input 30 of the device start, input 31 of the device stop, inputs 32 of device resource readiness, inputs 33 of the device resource type, outputs 34 of the device, control 15 inputs 35 of the nodes 25 and information inputs 36 nodes 25,

Each node 25 of the formation of the queue (Fig, 2) contains a group of shift registers 37, a group of elements AND .20 38, a group of elements OR-NOT 39, a group of elements OR 40 and a decoder 41.

The device works as follows.

The initial state of the device 25

characterized by the fact that triggers 10 and 11, registers 4, 24 and 37 are set to "0" (not shown, but).

If necessary, refer to 30

The device at the inputs 33 in the corresponding registers 27 are entered codes of resource types that are installed programmatically in a computing system. 55

On entries 28 in register 1, applications are received simultaneously with codes of type of applications on entries 29, which are received in the corresponding registers 24.

Depending on the ratio of the number of free and occupied resources, the device can operate in the following modes: formation of a queue of requests to different types of required resources, when all resources are occupied 45 (the first mode); transfer to service applications free resources • (second mode); queuing applications for different types of occupied resources and transferring applications to free resources (third mode),

The first mode. It is characterized by the fact that all bits of the register 4 are in the zero state. Zero signals from single outputs of bits ~ ~ register 4, elements 18 are closed.

Using subscriber selection nodes 19 for each queue forming node 25 of the same name is provided

the conversion of the discharge number of the buffer register 2 applications to the binary code of the subscriber number of this application.

Suppose that registers 1 received applications from subscribers, and registers 24 received binary codes of the required resources so that in the first registers they are placed in ascending order, and in subsequent registers in an arbitrary order. Each node 19 generates at the outputs of the encoder 23 a binary code of the subscriber number as follows.

Suppose that in registers 27 adopted binary codes of the resource type, placed in ascending order, i.e. The register 27 contains the binary code of the unit established for the first resource, the register 27 _g contains the binary code of the number two for the second resource, and so on.

The output signals of the registers 27 are fed to the first inputs of the comparison circuits 20 of the same-name nodes 19, and to the second inputs of these circuits - the output signals from the corresponding registers 24.

Since trigger 11 is in the zero state, the single signal from its zero output allows reception of information into register 2 from register 1 of applications. Consequently, by means of the buffer register 2, the status of the flow of applications entering the register 1 is monitored.

The operation of the device starts at the start signal, arriving at input 30 and setting trigger 1 into “1” and through element OR 8 trigger 11. At the same time, a single signal from the control input of register 2 is removed and the orders from subscribers received at that moment are recorded time in register 1,

Single signals from the outputs of the bits of the register 2 are open on the second inputs of the elements And 21 in all nodes 19

Since the first application requires the first type of resource and also the type of the resource can be set to any application, or several of them with numbers within the limits, then in node 19 ^ at the output of the comparison circuit 20 ^ and a number of others, single signals are generated arriving at the first inputs of elements of the same name And 21. These elements are opened with a single signal from the zero output for the first time5

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number of register 14 readiness resources. If, for example, besides the first subscriber, the first type of resource is needed by another, then the corresponding code is set at the outputs of the And 21 elements.

With the help of elements And 22, connected to the outputs of elements And 21 according to the priority scheme, the leftmost unit is distinguished, i.e. the unit with the output of the lower element number And 21.

In this case, at the inputs of the encoder 23, the positional code 15 is set 10 ... O, the output of which forms the binary code of the unit.

Similarly to the above, at the outputs of the encoder 23 of the second node 19, the binary code of the number 20 is two, and so on.

Binary codes from the outputs of the encoder 23 nodes 19 arrive at the elements And 26 of the same name nodes 25 forming the queue. 25

Elements And 26 open single signals from zero outputs of the corresponding bits of register 4, Therefore, a delayed pulse generator 12 delay element 13 passing 30 through the open element AND 14 single signals from single outputs trigger 10 and 11 and a single signal from the output of the element OR 3 is provided transfer of binary codes of subscriber numbers to nodes 25.

The formation of the queue at each of the nodes 25 is organized in the same way and is performed as follows. Since the registers 37 (figure 2) are set to "0", the output of the last element OR NOT is generated, a single signal by which the last elements of AND 38 of all groups are open, and the outputs of the remaining elements of OR-NOT ₅ 39 are set zero signals. Therefore, the binary code from the outputs 36 is received in the last bits of the registers 37. After the completion of the transients in the registers 37, the single signal from the output of the last element OR NOT 39 is removed. In this case, at the input of the penultimate element OR-NOT 39, a single signal is formed, which opens the penultimate elements AND 38 of all groups, and zero outputs are set at the outputs of the remaining elements OR-39. With this signal, two *

The actual code of the next subscriber requiring this type of resource will be recorded in the penultimate bits of the registers 37.

The output signals from the last bits of the registers 37 are fed to the decoder 41, which converts the binary code of the subscriber number to unitary. In this case, a single signal is formed at the output 34, the number of which corresponds to the number of the subscriber.

To eliminate the denial of service, the capacity of the registers 37 is chosen equal to the number of subscribers.

Simultaneously with the recording of binary codes of subscriber numbers in nodes 25, the delayed pulse of generator 12 from the output of the element 14 through the open first elements 17 of all groups are set by single signals from the outputs of the elements 21 and 21 of the nodes 19 the first bits of the register I, buffer, register 2 applications and through the element OR 9 - trigger 11. A single signal from the zero output of trigger 11 is allowed in register 2 to track the status of the flow of applications entering register 1.

The delay delay element 13 of the delay is determined by the time of transient processes in the elements of the junction 19. Since register 1 has applications, then the output of the element OR 3 holds a single signal ^ which element AND 7 is open at the first input. Therefore, the next generator pulse 12 through the open element, Ment AND 7 and element OR 8 trigger. 11 is set to one. After this, the process of transferring the binary codes of subscriber numbers to the registers of the 37 nodes 25 occurs similarly to that discussed above.

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If at the end of the queuing cycle the register 1 is in the zero state, a single signal from the output of the OR 3 element is removed. This closes the elements And 7 and 14, and on the inverse input opens the element And 6, which is the impulse of the generator 12 confirms * zero zero trigger value 11.

Element And 6 is necessary to reset the trigger 11 in order to eliminate the impact of the pulse generator 12 on the circuit elements of the device, when the arrival of the start signal, install-

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trigger I1 in one state, in register 1 there are no applications.

Second mode. Upon completion of service of the application. At the inputs 32, the device is given signals to release the corresponding resources, setting the same bits of register 4 to the state "1".

Let signals from all resources arrive at the same time. At the same time, single signals from the same outputs of register 18 are opened by single signals from the unit outputs of register 4. Simultaneously, zero signals from zero outputs of register 4 block the formation of binary codes of subscriber numbers in nodes] 9 and transfer them to form a queue at nodes 25 through elements 26 of all groups.

In this mode, the contents of the registers 37 in all nodes 25 are simultaneously shifted by the pulse of the generator 12 through the open elements 15 and 18. This pulse arriving at the inputs of the shift registers 37 shifts their contents by one bit towards the high bits so that The last digits set the binary code of the next subscriber.

Let a queue of applications be formed before the shift in all registers 37. Then after the shift in the first bits of the registers 37 is set to zero code. At the same time, since non-zero codes are recorded in all instrumental digits of registers 37, zero outputs are generated at the outputs of the Corresponding elements OR NOT 39, which arrive through the element OR 40 <at the corresponding input of the element OR-NOT 39, <

Since in the first digits of registers 37 there are zero codes, then at the output of this element a single signal is formed, which opens And 38 elements on the second inputs in all groups. This makes it possible to receive the binary code of the number of the next subscriber in the queue to this resource.

The second mode is completed by setting the register bits 4 to zero state by a generator 12 delayed element · delay 16 through open elements AND 5. The delay time element 16 is chosen so that by the time a delayed pulse appears, the first inputs of AND .5 result in shear transients codes in the registers of 37 nodes 25.

The third mode. This mode is characterized by the fact that when the service completion signals are received from a number of resources, the contents of the registers 37 shift in the corresponding queuing nodes 25, and the remaining queuing in the remaining nodes 25 is arranged.

Let, for example, from the first resource at the input 32γ in the first discharge of register 4 received a signal of its release. In this case, the zero signal from the output of the first discharge blocks the elements 21 at node 19, and the elements 26, node 25, thereby prohibiting the reception of the binary code of the subscriber number at node 25, the formation of the queue. In addition, elements 5 and 5 and 18 open with a single signal from a single output of the first digit of register 4, ensuring the transmission of a pulse from the generator 12 for shifting the codes in node 25, and damping the first digit of register 4.

Thus, in this mode, by the same impulse of the generator 12, the codes are shifted in nodes 25 in accordance with the incoming signals from the same released resources, and in the remaining nodes 25 - the formation of a queue to the required resources.

If necessary, change the codes of the type of resources in the registers 27 or disconnect the device at the input 31, a stop signal is given, by which the triggers 10 and 11 are set to zero states. Zero signals from the zero outputs of these flip-flops block the transmission of generator 12 pulses through elements 14 and 15. After changing the resource type codes, the device is reset and triggered by a signal on input 30.

Claims (1)

Claim Device.for the organization of access to resources, containing the register of applications, informational inputs of which are inputs of device requests, a group of registers of type 'applications, informational inputs of which are9 . 1488799 ten inputs of the type of requests of the device, the resource readiness register, the unit inputs of the digits of which are the device readiness inputs, the resource type register group, whose information inputs are the device resource type inputs, the group of queuing nodes · whose outputs are the device outputs, clock generator, two the delay element, the first trigger whose single input is the device start input, and the zero input is the device stop input, four AND elements, three OR elements, two groups The elements of And, η groups of K elements And, K groups of η elements And (where K is the number of resources in the system, η is the number of sources of queries), a group of K subscriber selection nodes, each of which contains a group of comparison circuits and the first group of elements And, moreover, the single input of the first trigger is connected to the first input of the first element And, the output of which is connected to the first inputs of elements And η groups by elements And, the outputs of elements And the first group are connected to zero inputs of the same name of the resource readiness register, single outputs of the categories connected to the first inputs of the same elements of the first and second groups, the zero output of each level of the resource readiness register is connected to the first inputs of the elements of the same name group from to groups of η elements, the outputs of which are connected to the information inputs of the corresponding group of the group forming the queue connected to the output of the element of the same name AND the second corpse, in each node of the subscriber selection of the group the first inputs of the comparison circuits of the group are combined and connected to the outputs of the same name register and resource circuits, the second inputs of the comparison group type connected to outputs of the application-type of the same name register group outputs the comparison circuits are connected to first inputs of the same name; elements And groups of your subscriber selection node, the second inputs of elements AND of the first group are connected to the output of the first delay element, whose input is connected to the second inputs of elements AND of the second group, characterized in that, in order to expand (functional capabilities due to the simultaneous formation of queues to heterogeneous resources, a buffer register of applications is entered into it, the second trigger, and the second group of elements AND and the encoder in each node of the group subscriber selection, the device’s start input connected to the first input of the first element OR, the stop input of the device is connected to the first input of the second OR element, the output of which is connected to the zero input of the second trigger, whose single input is connected to the output of the first OR element, the second input of which is connected to the output of the second And element, the first input of which is connected to the first direct the input of the third element And, to the input of the second delay element and to the output of the clock pulse generator, the output of the second delay element is connected to the second input of the first and the first input of the fourth And elements, a single output the first trigger is connected to the second inputs of the second and fourth And elements and to the second direct input of the third And element, the zero output of the second trigger is connected to the clock input of the buffer register of requests, the inputs of which are. connected to the outputs of the order register bits of the same name and to the inputs of the third OR element, the output of which is connected to the third inputs of the first and second AND elements and the inverse input of the third AND element, the output of which is connected to the second input of the second OR element, the third input of which is connected to the output of the first element I, the fourth input of which is connected to the unit output of the second trigger, at each node of the group subscriber selection, the output of the ΐth element I of the first group (ί = 2,3, ..., η) is connected to the direct input-th and to inverse last inputs The second element of the second group, the output of the first element of the first group of each node of the group’s subscriber selection node is connected to the first input of the encoder and the second 'input of the same name element of the first group of η groups of And elements; the outputs of the encoder of each group's subscriber selection node are connected to. the second inputs of the elements of the AND group of the same name from the second to the groups of elements AND, the zero output of each eleven 1488799 12 of the resource readiness register register is connected to the second inputs of the AND group of the same group of the subscriber selection node of the same name, the outputs of the buffer register register bits are connected to the third inputs of the AND elements of the same name of the first group of all the group subscriber selection nodes, and the output of the first AND element are connected to the third inputs elements And all groups from to groups of η elements And and with the reset input I of the buffer register of requests, outputs of elements AND in each group .from η groups of k elements AND combine 15 yens and are connected to the zero input of the order register of the same name, the outputs of the same name elements of the second group in each node of the subscriber selection group are connected to the second inputs of the AND elements of the same name from η groups of k elements And, starting with the second group, the output of the fourth element I is connected to the input of the first delay element, the outputs of the elements AND the second group in each node of the selection of subscribers of the group are connected to the inputs of the encoder. 1488799 2. y *