SU1479942A1 - Device for simulating change of net database capacity - Google Patents

Abstract

The invention relates to computing. The purpose of the invention is the expansion of the class of tasks. For this purpose, a simulation time control block, an address shaping block, vertex recorders, and an active vertex simulation block are entered into the device. The process of changing the size of a database is considered as a process of changing its generations. The simulation time control block is used to set and control the number of simulated database generations. The simulation is carried out as follows. In the address generation unit, the next memory location address is generated, defining the database modeling order. The process of generating segment instances is specified in the active vertex modeling block. The number of instances generated is random and the distribution characteristics are given in the memory block. 4 hp f-ly, 7 ill., 1 tab.

Description

one

The invention relates to computing, namely, to specialized stochastic models, and can be used in modeling databases.

The purpose of the invention is to expand the class of tasks to be solved by providing opportunities for modeling the process of changing the database size over time, represented as a change in the number of vertices in realizations of a random forest with a given height and topology, a random total number of vertices and generated by a random branch with a finite number of types particles.

Figure 1 shows a block diagram of a device for modeling.

changes in database size; figure 2 is a functional diagram of the recorder vertices; FIG. 3 is a functional diagram of the simulation unit ak. naive top; 4 is a functional block diagram of the simulation time control; Fig. 5 is a functional diagram of an address generation unit; 6 shows the structure of the second memory block; Fig. 7 illustrates an example of a process for changing the amount of a data base.

The device (Fig. 1) contains the address register 1, the simulation time control unit 2, the address generation unit 3, the first power supply unit 4, the decoder 5 of the active vertex number, the second memory unit 6, and

CO CO 4 b

encoder 7 of the generator vertex number, random number sensor 8, vertex registration unit 9 consisting of n vertex recorders, active vertex simulation unit 10, pulse generator 11, delay block 12

Block 9 of registering vertices is intended to simulate the process of growing the number of instances of vertices (segments) of n types and registering their number in each generation of the database and consists of n vertex recorders. Each recorder (Fig. 2) of the vertex contains the first trigger 13, the first element 14, the first group of elements 15, the adder 16, the second element 15, the register 18, the third group of elements 19 and the second trigger 20.

The active vertex modeling unit 10 (FIG. 3) is intended to implement the number of modeling cycles for generating new active vertex instances (segment) instances in the dannion database generation and contains a trigger 21, a counter 22 and a HE element 23.

The simulation time control unit 2 (Fig. 4) serves to set and monitor the number of simulated database generations and consists of a counter 24 and a group of elements And 25.

The address generation unit 3 (FIG. 3) is used to generate the next address of the memory cell in which information about the generator and active vertices (segments) numbers modeled in the given database generation is stored and contains trigger 26, pulse generator 27, counter 28 and element NOT 29.

Address register 1 is designed to store and output the maximum cell address of the first memory block 4.

The first memory block 4 is designed to store and issue the types of the generator i and the active j vertex segments of the database. An example of filling the first memory block 4 for a given logical database model is given in table „

The decoder 5 of the active vertex number, when a code of the active vertex number arrives at its input, outputs a single signal at the corresponding output.

The second memory unit 6 is designed to be stored and issued, when a signal arrives at its control input, to a set of probability values in accordance with a given address (ij) at the address input. The second block of 6 memory consists of n pages, 1 page corresponds to the i-th and

each vertex contains each addressable area corresponding to the jth active vertex. Each of the areas contains a certain number of cells. The number of filled cells in the area and their contents are determined by the distribution interval of the random variable oi, and the type of the distribution function F (cLJ), respectively.

Q Figure 6 illustrates the structure of the second memory block.

The random number sensor 8 generates random numbers oil (t) oi-. corresponding to the number of copies

5 segments of type X in the t + 1 generation, generated by one instance of a segment of type X; in the generation t, with probabilities | Poi, the values of which come from the output of the second memory block 6.

The generator 11 generates a pulse with a fixed period of following only at a zero signal at the input. The delay unit 12 delays the passage of a single pulse from the control output of the address generation unit 3 by a time interval sufficient to record the contents of the accumulator 16 of the accumulating type in register 18.

0

five

0

five

0

five

The pulse shaper 27 generates a single signal at the output when the signal at the input falls from zero to one.

H

To achieve this goal, the process of changing the size of a database containing a finite number of types X, Xg ... Xi of interconnected information components (segments) is considered as a process of changing generations of the database. The database state is described by a random vector (u (t) fU, (t), ..., (% (t)), the i-component of which (H; (t) indicates that at the moment c there is (U; (t Type X instances. The process of changing the size of a database is determined by the transition probabilities P Dt).

five

equal probabilities that one instance of a segment of type X; during time t goes (generates) into a set of segment instances corresponding to a random vector L (oij, ... j & J,) where -oi is the number of instances of a segment of type oij, is the number of instances of a segment of type X „.

In this case, the probability P (t) can be represented as P, (t)

“,

 P Poij, where is the probability j i j j

the fact that one instance of a segment of type X generates a collection of instances of a segment of type X, equal to oij, where oij 0, 1, ....

At the next time instant t + 1, each of the existing instances of segment X, where i, 111, can generate a random number (t) of instances of segment Xj, for which the probability distribution is P {oi.Ht) oi P0, where oL 0 , -1, ..., and the database size will be equal to U (t + 1) (III, (t + 1), ..., J44 (t + 1)), where / u: (t + n Mt ). ,

+ about Z g.e jk specific value of s. generated instances of a particular instance of fU | (t).

Fig. 7 illustrates an example of a process for changing a database volume for a logical model from a table for | U (0) (2.2,1,1).

Each of the database generations can be represented by the implementation of a random forest with a given topology and height — defined by a logical database model, and a random number of vertices determined by the interval of distributions of values

nonlocum ot (t) and simulation time t.

0

To characterize a random forest, a branching random process with a finite number of particles can be used, which is a series of values (U (t)).

When modeling the change in the database volume (Fig. 7), the device operates as follows. Before starting the simulation, the contents of the registers of the 18 vertex recorders are equal to the initial number of instances.

5 segments fU (t) (| U, (t),), Uh (t) of types X ,, Xa,. “., Xh respectively at time t 0. The contents of register 1 address is equal to the value of the maximum cell address of the first block 4 memory

The triggers 13, 20, and 21 are in zero, and the trigger 26 is in one state. The contents of counter 24 are equal to the number of simulated generations of the database n, the contents of adders 16 and counter 22 are zero, and the first control input of counter 24 is given a signal of a logical unit.

° Since the output of counter 24 (Fig. 4) is signal 1, and the trigger is in one state, the contents of register 1 of the address will be written to the counter. 28

5 (FIG. 5), after which the O signal at its output transfers the trigger 26 to the zero state and the signal 1 from its zero output will allow information to arrive at the reading input of counter 28. The content of counter 28 goes to the address input of the first block 4 the memory and causes the readout from its memory cell with the address 7 of the code of the number on the 5th generating vertex 1 and the code of the number of the active vertex 1. The code of the number of the active vertex supplied to the input of the decoder 5 (figure 1) causes the appearance of the first information

0 input of the vertex recorder with the number 1 of the signal registration module of the vertices 1, which translates the trigger 13 of the first vertex recorder into a single state, and a single signal

5 from the single output of the trigger 13 permits the recording of information in the accumulator 16 of this vertex recorder.

The code of the generating vertex number applied to the input of the decoder 7 causes the appearance at the second information input of the vertex recorder number 1 of the signal registration block of the signal H, which translates the trigger 20 of the first recorder into a single state, and a single signal from the single output of the trigger 20 hinders reading the initial number of instances of W, (t) of segment X of re-Q

the horn 18 into the counter 22 of the active vertex modeling unit, after which the output of the counter 22 is a signal O, which translates the trigger 21 into a single state, as a result of which information is received at the subtracting input of the counter 22, the reception of the information is prohibited to informational inputs

the counter 22 and the generator 20 11 of the pulses is started, single pulses from the output of which transfer the triggers 20 of all the vertex recorders to the zero state, which leads to the prohibition of reading information from the registry 18 of the active vertex. Each single pulse from the output of the generator 11 pulses causes reading from the second memory block 6 in accordance with the address given at its input with

memory block 4, sets of probi

(with Pci | s in the specific case

{Poi} (5 which are fed to the input of the random number sensor 8, which produces a random number oi, which is fed to the input of the adder 16 of the first vertex recorder. This same single signal reduces the content of the counter 22 by one.

As soon as the contents of counter 22 become zero, a 1 signal appears at its output, the occurrence of which permits the reception of information to the second information input of counter 22, putting the trigger 21 into the zero state, prohibits the operation of the pulse generator 11 and the driver 27 of the pulses The address generation unit generates a single pulse, which reduces the contents of counter 28 by one. Thus, the simulation of the first active vertex is completed, in Fig. 7 this corresponds to the situation of generating new instances of segments of type 55. Instances of segments of type X, this situation is specified in the cell with address 7 of memory block 4.

thirty

35

40

 45

50

Q

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20 25

55

thirty

35

40

45

50

After completion of modeling all generating situations specified in memory block 4, i.e. As soon as the contents of counter 28 become zero, a signal 1 appears at its control output, which, when it arrives at the second control input of the vertex registration unit, allows the contents of adders 16 to be read into registers 18 of all vertex recorders, and passed through delay block 12 , sets the triggers 13 to the zero state and zeroes the contents of the adders 16. This same signal 1 from the output of the counter 28 reduces the unit of the counter 24 by one, and also, by switching the trigger 36 to one, allows the information to be received by the counter 28 1 of the register address. This concludes with the simulation of the first generation of the database; as a result, the registers 18 of the vertex recorders contain the vector U (t + 1) ((H, (t + 1), (Uj (t + 1), ..., fUn ( t + l)). Next, the simulation of the next generation of the database begins. The described procedure repeats until the contents of counter 24 become zero, which will reset the signal 1 at its output and prohibit the next reading of the address from register 1 of the address This is where the simulation ends, and the registers 18 of the vertex registration unit contain the vector (U (t) (fU, (t + 1), / U4 (t), ..., (Un ( t)), for t p, where n is the number of simulated database generations

Claims (5)

1. A device for simulating a change in the size of a network database, comprising a pulse generator, a first memory block and a second memory block, the outputs of which are connected to the inputs of a random number sensor setting, characterized in that, in order to expand the class of tasks to be solved by enabling modeling the process of changing the database volume over time, n vertex recorders are entered into it, the active vertex modeling block, the number vertex-i decoder of the active vertex, the decoder of the parent vertex, b-s s-irc-i 914 ki, simulation time control block, address shaping block and address register whose outputs are connected to the corresponding information inputs of the simulation time control block whose outputs are connected to the corresponding information inputs of the address generation block whose information output group is connected to the corresponding address inputs of the first memory block ti, the first group of outputs of which is connected to the corresponding inputs of the decoder of the number of the active vertex of the 1st (, 2, ..., n) whose output with the first information input of the 1st vertex recorder, the outputs of all the vertex recorders are integrated into the data bus and connected to the corresponding information inputs of the active vertex modeling unit, the output of which is connected to the control input of the address generation unit and to the input of the pulse generator whose output is connected to the control input of the active vertex modeling block, to the synchronization input of the second memory block and to the vertex blocking inputs of the vertex recorders, a group of information inputs to Each of which is connected to the corresponding outputs of the random number sensor, the second group of outputs of the first memory block is connected to the address one, respectively. to the inputs of the second memory block, the third group of outputs of the first memory block is connected to the corresponding inputs of the decoder of the generating vertex number, the 1st output of which is connected to the second information input of the 1st vertex recorder, the output of the address generation unit simulation, with the entries of the recording of the vertex recorders and through the delay block with the inputs for resetting the activity of the vertex recorders. 2. The device according to claim 1, characterized in that each vertex recorder contains two groups of elements AND, an adder, a register, two elements NOT and two triggers, a group of information inputs of the vertex recorder connected to the first inputs of elements AND of the first group whose outputs are connected jc inputs 994210 adder, the outputs of which are connected to the data inputs of the register, the outputs of which are connected to the first inputs elements And the second group, outputs five which are the outputs of the vertex recorder, the first information input of which is connected to the single input of the first trigger and through IQ is the first element NOT to the first zero input of the first trigger, the output of which is connected to the second inputs of elements AND of the first group, the second information input of the bus recorder ver15 is connected to the single input of the second trigger and through the second element NOT to the first zero input of the second trigger, the output of which is connected to the second inputs of the elements And 2Q of the third group, the second zero input of the second trigger is the vertex blocking input of the vertex recorder, whose recording input is connected to the register synchronization input, input 25 reset the activity of the recorder vertex connected to the second zero input of the first trigger and the reset input of the adder. 3. The device according to claim 1, about tl and - 30, in that the active vertex modeling block contains a NOT element, a trigger and a counter, the initial installation inputs of which are connected to the information input of the block, the control input of which is connected to the counter count input, the output of the zero state indication of which is connected to the output of the block, with the zero input of the trigger and through the element NOT . with a single trigger input, the single and zero outputs of which are connected respectively to the counting input input and to the meter enable input input. 4. The device according to claim 1, about tl, which is that the address generation unit contains a pulse shaper, a NOT epement, a trigger and a counter, the outputs of which are connected by a group of information outputs of the block, the control input of which is connected via a pulse shaper to the counting input a counter whose zero-state indication output is connected to the output of the block, with a single trigger input and through an element NOT with a zero trigger input, the single and zero outputs of which are connected respectively to the input 35 45 50 55 eleven permissions to the inputs to the resolution enable of the counter, whose data inputs are the information inputs of the block. 5. The device according to claim 1, of which is that the simulation time control block contains a counter and a group of elements, the outputs of which are outputs 7994212 block whose time entry connected to the counter input of the counter, the inverse output of the zero state indication is connected to the first inputs of the 5 elements AND groups, the second inputs of which are information inputs of the side, the installation input of the block is the input of the initial state of the counter. From d / f, 12 From fa J From fa, 11 FIG. 2 to fan about- From fa tO O- 27 From 6l. 2 ABOUT- / 7i L f-d  D L "" U / & / n5l.2,12.9 - O nvl.4 -o 1JL / Ј0 figs ri & .6 " ЈL (M 3 in R V ms and it  H