SU1478336A1 - Relative zero-code-to-binary converter - Google Patents

Abstract

This invention relates to automation and computing. Its use in the systems of reading, converting and transmitting information allows to expand the functionality by extracting the clock signal and improving the noise immunity in the case of an unstable repetition period of the input signal. The converter contains a block of edge selection 1, counter 4 and element I6. By introducing the generator 3, the decoder 5 and the output signal generating unit 2 with the corresponding performance in the converter, stable operation is ensured. 1 hp f-ly, 4 ill.

Description

figure 1

114

The invention relates to automation and computing and can be used in systems for reading, converting and transmitting information.

The purpose of the invention is to enhance the functionality by allocating a clock signal and increasing noise immunity in an unstable period of repetition of the input signal.

Figure 1 presents the functional diagram of the Converter; Fig 2 is an output signal generating unit; FIG. 3 shows signal timing diagrams; Fig. 4 is a graph of the operation of the output signal generating unit.

The converter contains (Fig. 1) an edge extraction block 1, an output signal shaping block 2, a pulse generator 3, a counter 4, a decoder 5 and an AND 6 element. In Fig. 1, information input 7, input 8 of the initial installation, information and clock outputs 9 and 10,

The edge extraction unit 1 serves to generate pulses coinciding with the edges of the input signal. It can be made in the form of a differentiating element connected in series and a generator of positive pulses.

The output signal shaping unit 2 contains (FIG. 2) the first - third triggers 11-13, the first and second decoders 14 and 15, the first - the third elements AND 16-18 and the first - the eighth elements OR 19-26. Fig. 2 denotes the first and second information inputs 27 and 28 and the control input 29,

A converter with this execution of block 2 converts the Manchester I code to a non-return code (LBH). In the case of converting the Manchester II code to the LBH code to the inputs of the And 18 element, instead of the specified ones, the direct trigger output 13 and the inverse trigger output 11 are connected.

On fig.Z marked diagrams: a - convertible information (code BVN); b - relative zero code (ONK), in this case Manchester I; in - a signal on an entrance 8; g - signal at the output of the generator 3; d - signal X at the input 27 of block 2; e - signal Z at the input 29 of block 2; W - signal Y at the input 28 of block 2; h - signal at output 9; and - signal

Q

g

0 5

about

P

0 5

five

362

exit 10; k - numbers of states of block 2 in the graph of fig. 4.

The converter to binary code works as follows,

A PMC carrying binary information, for example 1010011, is fed to the input 7 of the converter,

For definiteness, let us present the principle of encoding binary information in the POC such that symbol 1 corresponds to the repetition of the previous coding element, and symbol O corresponds to a hint of the coding element to the opposite. The coding element is determined by which of the halves of the information following period T1 is given a single (zero) level,

From the output of block 1, a sequence of positive pulses synchronous with the fronts and sections of the PMC is fed to the input 27 of block 2, thereby a signal X is generated, which also goes to the R input of counter 4,

The generator 3 generates a sequence of positive pulses with a period T2, which are fed to the C input of counter 4 and one of the inputs of element 6. The group of outputs of counter 4 is connected to the information inputs of the decoder 5, the pth output (n2-2, where k is 4) of the decoder 5 is connected to the second input of the element 6 and the control input 29 of block 2, if the counter 4 in the interval between two adjacent pulses at its R input has time to count n pulses with a period T2, then the output of the decoder 5 has a Wits signal permission to skip (n + 1) -g pulse with period T2 from generator 3 element And 6. Thus, at the output of element And 6, a signal Y is formed, which is each (n + 1) -th pulse with period T2 after the last pulse at input 27 of block 2 and at R - input of counter 4,

The control unit 2 (FIG. 2) operates in accordance with the graph (FIG. 4) and generates a potential binary serial code at output 9 and conversion steps at output 10. States j - k of flip-flops 11-13 are treated as a three-bit parallel binary code which has the youngest first bit implemented by the first j - k trigger 11, the second bit the second j - k trigger 12 and the older third - the third j - k trigger 13. Kodirova

The understanding of the states is indicated on the verines of the graph by decimal digits corresponding to this three-digit binary code. Switching the states j - k of the flip-flops 11-13, connected by the R- and C-inputs, occurs over a slice of the pulsed signal of the chiu, coming from the output of the element OR 19 depending on the potentials at the j-k inputs of the flip-flops 11-13.

The initial setup signal from input 8 j - k triggers 11-13 are set to the zero state (zero vertex of the graph). The three-digit code from outputs j - k flip-flops 11-13 enters the information inputs of the decoders 14 and 15. From the output of the zero bit Yes, the decoder 14 transmits the unit potential to the first input of the element OR 20 and then from its output to the J input of the first trigger 11, the remaining five j - k inputs of the trigger 11-13 contain a zero potential. After a cut-off of the initial setup signal X, the first trigger 11 is switched to state 1, which corresponds to the transition in the graph. At the output of the first discharge of the decoder 14, a single potential arises; at the remaining outputs, it is zero. At the output of the element OR 20, the zero potential is restored, at the output of the element OR 21 — a single across the second pulse X, the third trigger 13 switches to state 1. On the graph, transition 1 occurs. Since the time interval between the first and second pulses X is T1 / 2, the counter 4 will not have time to count n pulses of the period T2 during this time, and the pulse signal Y at the input 28 of block 2 will not occur.

Under the influence of the 3rd and 4th pulses X, following with the same time interval in the half-period of information arrival, transitions occur, the Next 5th pulse X follows with an interval T1, and in the interval between the 4th and 5th m pulses X at the output of the decoder 5, a signal Z is generated, and at the output of the element 6, a pulse Y, the signal Z at the input 29 of block 2 turns off the decoder 14 and connects the decoder 15, From the output of the seventh digit of the decoder 15, the unit potential through elements OR 25 and 22 enters

0

five

0

 . 50

0 5

0

K-inputs of the first and second flip-flops 11 and 12, On the slice of the pulse Y, the transition occurs 7 4. Similarly, the subsequent switchings in block 2, indicated on the timing diagram, occur.

The need to use the decoder 15 is caused by the need of block 2 to distinguish between signals X and Y, affecting the triggers 11-13 along a single circuit in the 5th - 7th states, and to make transitions defined by the graph.

The output signals of block 2 are generated using an element AND 18 and elements AND 16, 17 and OR 26. The signal at output 9 receives a single potential when block 2 is in the 3rd or 7th state. The pulse signal at output 10 is synchronous with the signal X and is formed by gating the signal X by the 3rd and 4th states of block 2,

Since the information being transformed to the input 7 from mechanical devices, as a rule, has an unstable period of following T1, when choosing the parameters n and T2 of the converter, this instability should be taken into account. Due to the asynchrony of the pulses T2 with the frequency of arrival of the transformed information, it is required that the nn period of the pulses T2 be entirely located within the second half period of the transformed information, i.e.

(n-1) iT1-A,

where d - maximum instability

period T1, From here

„.-.

Claims (2)

As follows from the second inequality, the increase in instability -l can be compensated by reducing the period T2 of the generator 3 pulses. Thus, in comparison with the known converter, the proposed additionally generates a clock signal synchronous with the converted binary code, and can function in the extended frequency range, as well as the instability of the arrival period of the code being converted. Invention Formula 1, Relative zero-to-binary converter containing an edge extraction unit, a counter and an AND element, characterized in that, in order to expand the functionality by allocating a clock signal and increasing noise immunity in an unstable — repetition period of the input signal, an output signal shaping unit, a decoder and a pulse generator are inserted into the converter, the output of which is connected to the first input of the element And and the counting input of the counter, the outputs of which are connected to the inputs of the decoder, the output of which is connected to the second input of the element K and the control input b Forming output signals whose initial setup is the converter input of the same name, the input of the edge selection block is the information input of the converter, the output of the edge selection block is connected to the first information input of the output signal shaping unit and the counter zeroing input, the output of the And element is connected to the second information input input block of output signals, the first and second outputs of which are respectively information and clock outputs of the converter . 2. The converter according to claim 1, characterized in that the block forming output signals co10 15 The first flip-flop is connected to the wider inputs of the first and second decoders and the third element, And the output of the second trigger is connected to the second inputs of the first and second decoders and the third element, whose output is the first output of the unit, the output of the third trigger is connected to the third inputs of the decoder , the outputs of the zero second bits of the first decoder are connected to the first inputs of the second to fourth elements of OR, respectively, the output of the third bit of the first decoder is connected to the second inputs of the first element AND and the third element OR, the output of the fourth bit of the first decoder is connected to the second input of the second element AND and the first input of the fifth element OR, the output of the fifth bit of the first decoder is connected to the second input of the fifth and first input of the sixth element OR, the output of the sixth bit The first 25 decoder is connected to the second inputs of the second and sixth elements OR, the output of the seventh bit of the first decoder and the fifth and sixth bits of the second decoder are connected respectively to the third input of the sixth, first input of the seventh and second input the fourth element OR, the output of the seventh bit of the second decoder is connected to the third input quarter and the second input of the seventh element 20 thirty holds triggers, decoders, element- 35 OR, outputs of the second and seventh, n 10 15 83366 The first flip-flop is connected to the W-bins of the inputs of the first and second decoders and the third element, And the output of the second trigger is connected to the second inputs of the first and second decoders and the third element, whose output is the first output of the block, the output of the third trigger is connected to the third inputs of the decoder, the zero-second outputs of the first decoder are connected to the first inputs of the second to fourth elements of OR, respectively, the third discharge of the first decoder is connected to the second inputs of the first And element, and a third its element OR, the output of the fourth bit of the first decoder is connected to the second input of the second element AND and the first input of the fifth element OR, the output of the fifth bit of the first decoder is connected to the second input of the fifth and first input of the sixth element OR, the output of the sixth bit of the first 25 of the decoder is connected to the second inputs of the second and sixth elements OR, the output of the seventh bit of the first decoder and the fifth and sixth bits of the second decoder are connected respectively to the third input of the sixth, first input of the seventh and second inputs the house of the fourth element OR, the output of the seventh bit of the second decoder is connected to the third input of the fourth and second input of the seventh element 20 thirty You AND and OR elements, the first input of the first element OR is combined with the first inputs of the first and second AND elements and is the first information input of the block, the second input of the first OR element is the second information input of the block, the output of the first OR element is connected to the WALTHES of the first - third flip-flops, the R-inputs of which are combined and are the input of the initial installation of the block, the output of The first and third, third and sixth OR elements are connected respectively to the J and K inputs of the first to third triggers, the inverse control input of the first and the forward control input of the second decoder are combined and are the control input. the block, the outputs of the first and second elements AND are connected to the inputs of the eighth element OR, the output of which is the second output of the block, Compiled by S. Revinsky Editor N. Lazarenko Tehred M. Khodanych Order 2372/54 Circulation 885 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5 Production and publishing complex Patent. Uzhgorod, st. Gagarin, 101 Proofreader M.Vasilyeva Subscription