SU1469555A1 - Device for assessing channel pulse response - Google Patents

Abstract

The invention relates to communication technology. The purpose of the invention is to improve the accuracy of estimating the pulsed x-channel. The device contains linsho of delay 1, accumulating cz mmators 2, keys 3, adders 4, multipliers 5, control unit 6 and unit of comparison and selection 7. A signal is received at the input of the device, which is an alternation of the probe and information signals generated from the same binary characters. The device determines the response of the channel to a single binary symbol that is transmitted in the probing signal, as well as determining the temporal position of the probing signal relative to the cycle period generated on the receiving side. Initially, the device operates in the pre-accumulation mode (or in the synchronism acquisition mode), and subsequently in the tracking mode. 1 il. (L

Description

The invention relates to communication technology and can be used in data transmission systems over channels with intersymbol interference with sounding the communication channel with a test pulse. /

The purpose of the invention is to improve the accuracy of the assessment.

The drawing shows a structural electrical diagram of the described device.

A device for evaluating the impulse response of a channel contains a delay line 1, P accumulating adders 2, P keys 3, P adders 4, P multipliers 5, a control unit 6 and a comparison and selection unit 7. Each accumulating adder 2 contains a binary counter 8, a demultiplexer 9, an adder 10, Q capacitors 11 and a voltage divider 12.

The device operates as follows.

To assess the response of the channel to the probing signal (impulse response) at the receiving side, it is necessary to determine the readings of this channel response and its temporal position in the cycle, i.e. Together with the task of evaluating the samples of the impulse response of the channel, the cyclic synchronization problem is solved. This determines the specifics of the operating modes of the device, namely: initially, the device operates in the preliminary accumulation mode (or in the mode of entering synchronism), and subsequently in the tracking mode.

In the initial accumulation mode, the signal fills all the elements of the delay line 1, and the delay time of each element is a multiple of T, where T is the clock interval of the probing and information binary symbols, and with the beginning of the reference period, the signals from the outputs of the delay line 1 arrive at the corresponding accumulating adders 2, namely, to the corresponding demultiplexers 9, 'to the gate inputs of which a pulse is supplied from the output of block 6. The address of the corresponding output from the binary count is received at the other inputs of the demultiplexer 9 ika 8. With each pulse cycle capacitor 11 at the next address stored reference signal and the sum in the adder 10 with the readings, E afterwards registered in previous cycles. After several cycles, at the outputs of those adders 10, in which the samples corresponding to the probing signal are added, reliable estimates of the samples of the channel impulse response are formed. At the outputs of other adders 10, which add up the samples corresponding to the information signal, a zero potential is formed due to the random nature of the transmitted information. Thus, at the outputs of several adjacent adders 10, estimates of the channel impulse response samples are formed. The number of nonzero samples (i.e., duration) of the channel impulse response can be different for each specific channel.

Since the impulse response of the channel can begin with any of the outputs of the delay line 1, the samples from the output of each of the adders 10 are analyzed. The samples from the outputs of the adders 10 are fed through voltage dividers 12 to the multipliers 5, where they are squared. The squares of samples from the output of each multiplier 5 are fed to the corresponding adder 4. From the output of each adder 4, the sum of the squares of the samples is fed to the inputs of block 7 of comparison and selection. Obviously, the maximum value of the sum of the squares of the samples will be at the output of the adders 4, the inputs of which receive the squares of samples corresponding to the impulse response of the channel. Block 7 comparison and selection analyzes the levels of samples arriving at its inputs, and determines the first of those at which the value of the sample is maximum. Block 7 comparison and selection at its outputs generates a signal that is supplied to the control input of the corresponding key 3. Shreds 3 with their other inputs are connected to the outputs of the respective voltage dividers 12. Upon receipt of the signal key 3 from the comparison and selection unit 7 at the control input, key 3 passes the signal from its inputs, at which point samples of the channel impulse response were formed to the second output of the device. At the first output of block 7 (the first output of the device), pulses are formed, 1 corresponding to the beginning of the pulse characteristic of the channel. In tracking mode, block 7 monitors the repeatability of the maximum count at the output of one of the adders 4. If, due to a mismatch or instability of the generators at the receiving and transmitting sides, the maximum count is offset, then block 7 generates a signal for connecting the previous or subsequent key 3 and on the first the output of the device produces a pulse corresponding to the new beginning of the impulse response. If the shift of the maximum countdown occurred by more than one clock, the device switches to the initial accumulation mode.

Claims (1)

Claim A device for evaluating the impulse response of a channel, containing a delay line, the input of which is the input of the device, P multipliers and an adder, characterized in that, in order to improve the accuracy of the evaluation, a comparison and selection unit is introduced, the first output of which is the first output of the device, P- 1 sum of tori, П keys, the outputs of which are combined and are the second outputs of the device, a control unit and 5 П accumulating adders, each of which contains Q capacitors AND series-connected binary counter, demultiple sor, adder and voltage divider, the output of which is the output of the accumulating adder, the first input of which is the first input of the demultiplexer, the outputs of which are connected to the common bus through the corresponding capacitors, and the second input is combined with the input of the binary counter and is the second input of the accumulating adder, line outputs delays through the corresponding accumulating adders are connected to the corresponding inputs of the corresponding keys, the outputs of the multipliers through the corresponding adders are connected to corresponding to the first inputs of the comparison and selection unit, the second outputs of which are connected to the control inputs of the corresponding keys, the second input is combined with the second inputs P of accumulating adders and connected to the first output of the control unit, the second output of which is connected to the third input of the comparison and selection unit.