SU1451732A2 - Multiplication/division device - Google Patents

Abstract

The invention relates to automation and computing and can be used in the processing of signals represented in code and pulse-width forms for better results of calculations in code and pulse-frequency forms. The purpose of the invention is to expand the functionality of the device by presenting a divider with the sum of two pulse-width signals. The multiplying-dividing device contains a reversible counter 1, elements AND 2, 3, 14, binary frequencies 4, 5, elements OR 12, 13, inputs and outputs of the device. The device is based on the principle of latitude modulation of pulse-frequency sequences and their automatic compensation using negative feedback when averaging the generated sequences and the presence of a pulsed stream, combined and separated in the process of creating feedback signals, resulting in a reproduction of rational Functions of three variables. 1 il. (L

Description

 L

h

Do

 14)

The invention relates to automation and computing technology and may find application in processing signals represented in code and pulse-width forms when computational results are obtained in code and pulse-frequency forms;

The purpose of the invention is to expand the functionality of the device by presenting the divider with the sum of two pulse-width signals.

The drawing shows the functional diagram of the proposed device

properties.

The multiplying-dividing device contains a reversible counter 1, elements 2 and 3, binary multiplies, 4 or 5 frequencies, scale input 6, input 7 of the first reference frequency, input 8 of the first pulse-width signal, device code output 9, frequency The device code 10, the input 11 of the second pulse-width signal, the OR elements 12 and 13, the third element AND 14, the input 15 of the third pulse-width signal, the input 16 and the input 17, respectively, of the second and third reference frequencies.

The multiplying-dividing. The device works as follows.

At the initial moment of time, the counter 1 is reset, the binary code N is input to the device 6, pulse width signals with one repetition period and relative durations 0 ,, QI are received at inputs 8, 11, and 15, respectively, and at inputs 7 , 16 and 17 are the reference pulse sequences with Foi and FOS frequencies shifted in time relative to each other by a third of the period to ensure the normal operation of the device.

The first impulse that occurred under the influence of the N code at the output of the binary multiplier 4 frequency, during the time interval of unlocking the element 2, passes to the output of the last one and is written into the reversible counter 1. Binary multiplier 5 starts to generate the pulse sequence, as the counter code 1 becomes different from zero, and its frequency input receives a pulse sequence from the output of the element OR 12 with a total frequency

 FOI due to the separation in time of incoming signals at its inputs. The impulse stream from the output of the binary frequency multiplier is further divided into elements AND 14 and 3 into two pulse sequences in accordance with the phase of the signals from inputs 17 and 16, respectively, for the feedback circuit of the device. At the same time, the selection of pulse sequences by pulse-width signals with relative durations in in in and followed by summing by the element OR 13 occurs at the same time.

The device is based on the principle of pulse width modulation of frequency-pulse sequences and their automatic compensation using negative feedback when averaging the generated sequences and the presence of a pulse flow combined and divided in the process of creating feedback signals, resulting in It produces a fractional rational function of three variables. The condition of the dynamic equilibrium of the device is the equality of the increments of the codes of the summing and subtracting circuits of the reversible counter during the repetition period of the pulse-width signals, i.e. the equality of the average frequencies of the pulse sequences arriving at its summing and subtracting inputs. I

The output element And 2 receives a pulse sequence with a medium frequency

F ,, ,,

where n is the size of binary frequency multipliers and a counter. Finding a binary frequency multiplier in the feedback circuit of the device allows to form a sequence of signals at the output of the AND 14 element from its pulse stream

Fob

2

F3 - N:

 J 1

where Nj is the code value of the reversible counter 1.

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Similarly, at the output of the element And 3 a pulse sequence is formed with an average frequency

- 2i N

J - -YY M

at,

 2n Z The condition of dynamic equilibrium of a device expresses equality

F, F2 + F, or

No., -f, u

e.

Rose

2

equality (,, FO ,; FOSJ N9,

(one)

Fz

(2)

In this case, the frequency output 10 of the device will receive a pulse sequence with an average frequency

FOJ N6,

  + in

Thus, introducing the third argument 65 into the denominators of dependencies (1) and (2) provides an extension of functionality. Lack of input of the third pulse-width signal with relative

0

five

0

25

ZO

32

; with each other, 0j preserves the form of functions reproduced by the prototype.

Claims (1)

Invention Formula A multiplying-dividing device according to the author, No. 788128, characterized in that, in order to expand the functionality of the device by presenting the divider as the sum of two pulse-width signal signals, two OR elements and a third AND element connected to the first input are introduced into it to the input of the third pulse-width signal of the device, and the second input to the input of the third reference frequency of the device and the first input of the first SHS element, the second input of which is connected to the third input of the second And element and the input of the second reference frequency stroystva, and output - with an input of the second binary frequency multiplier, the output connected to the third input of the third AND gate, the output of the second AND gate is connected to the subtraction input of down counter via a second OR gate, the other input of which is connected to the output of the third element I.