SU1450121A1 - Device for measuring delta-codec quantizing noise - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to improve the measurement accuracy, the device contains encoder 1, shift registers 2 and 11, decoders 3 and 4, amplifier 5 subtraction unit (HB) 6, voltmeters 7-9,; .. D-flip-flop 10, zl-t OR 12, inverter 13, PLNs AND 14 and 15, keys 16 and 17, threshold unit 18. The input speech signal after the auxiliary delta transform enters BV 6, where it is mapped to the delta codec signal 19. As a result, a signal is generated the difference that goes to the voltmeter 7, as well as to the information inputs of the keys 16 and 17. The key 16 (17) is 1m 1t only when in the difference ignale noise component present crushing (overload) which is measured by the voltmeter 8 (9), allows the voltmeter 7 to measure the total power of the quantization noise yl 2. with (/

Description

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The invention relates to radio engineering and can be used in the development and operation of communication systems with delta modulation.

The purpose of the invention is to increase measurement accuracy.

Figo 1 shows a structural electrical circuit of the proposed device; on fig2 - epures for the same time, which give details of his work

A device for measuring quantization noise of a delta codec contains encoder 1, first shift register 2, first 3 and second A decoders, amplifier 5, subtraction unit 6, first ,, second 8 and third 9 voltmeters, D- trigger 10, second register The 11 shift element OR 12, the inverter 13, the first and second elements AND 14 and 15, the first 16 and second 17 keys, the threshold block 18, also shows the delta codec 19 under study, consisting of the delta encoder 20 and the delta decoder 21.

The device works in the following way.

The investigated delta codec 19 is a serially included delta encoder 20 and delta decoder 21 (FIG. 1). It introduces delays and distortions in the input signal, therefore the signal at the output of the delta decoder 21 does not exactly correspond to the signal at the input of the delta encoder 20. To eliminate the delays of the signal in the investigated delta codec 19; as well as the difference in the signal levels at its input and output, you must enter the auxiliary delta conversion of the input speech signal S (t) (Fig.2A) using the delta codec consisting of the first shift register 2, encoder 1, first decoder 3, second decoder 4 and amplifier 5o. F sampling rate. This delta codec is chosen very high compared to the sampling rate of the investigated delta codec 19o. The high-speed binary DM signal from the output of encoder 1 supplies the second decoder 4, whose output signal contains negligible quantization distortion, since the sampling frequency F is high enough the first shift register 2, after which it is also decoded by the first decoder 3, the signal at the output of which is identical to the signal at the output of the second 25

five

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15 a, 20 k a- a

30 35 40 45 Q "j of encoder 4, BUT will be delayed relative to it for a time interval n / 1-, where m is the number of bits of the first shift register 2 of the Investigated delta codec 19, the noise at the input of which is measured, operates with a normal clock frequency F, Decoded analog signal S Ct) (FIG. 2a) at the output of the delta codec 19 under study (output of the delta decoder 20) differs from the input signal S (t) due to the noise introduced by the delta transform. This noise is much more noise, VNOSH. 1X in encoder 1 and in first decoder 3, and therefore signal S4t) is different from signal S (t). Next, the signal S (t) is mapped to the delayed signal S (t), as a result of which a difference signal is generated (Fig. 2b), which is measured by the first voltmeter 7 with a square-law characteristic. The amplifier 5 with a variable gain as well as the first shift register 2 serves to minimize the readings of the first voltmeter 7 Next, the difference signal from the output of subtraction unit 6 is fed to the input of the threshold unit 18, as follows: If the signal level at its input is greater than zero, then Signal 1 is present at the output of threshold unit 18, if the signal level at the input of threshold unit 18 is less or equal to zero, then Log.O signal is present at its output (Fig. 2c). Next, this signal is fed to the information input of the D-flip-flop 10, the synchronous input of which is connected to the input of the low clock frequency (Fig. 2d). Then the binary signal () is fed to the information input of the second shift register 11, the sync input of which is also connected to the low clock frequency bus (figure 2 g).

The criterion for separating overload noise from crushing noise is the presence of a bursts of pulses in a binary signal (Fig. 2d) consisting of n-after; coded signals 1 "1 waves 1 or O characters. The number n corresponds to the number of bits in the second register 11 shift and is selected depending on the clock frequency of the investigated delta codec 19. The number n is chosen within

2 n 5.

;

When filling out all the n-bits of the second register 11 shift characters

H or symbols O at the output of the first element AND 14 or the second element AND 15, respectively, appears the signal. Otherwise, i.e. if at least one signal of Log.O is present on one of the p-inputs of the first element AND 14, and at least one Log.1 is present on one of the p-inputs of the second element 15, a signal is present at the outputs of these elements 14 and 15 Log Next, the signals from the outputs of the first and second elements AND 14 and 15 (Fig. 2e, g) are fed to two inputs of the element OR 12, where they are combined (Fig. 2h) o Signal Log. G from the output of the OR 12 element is unlocking for the second key 1 7 and locking for the first key 16, since it is fed to it through the inverter 13. Therefore, if the signal of Log.1 is present at the output of the OR 12 element, then the first key 16 is closed , and the second key 17 is open, if at the output of the element OR 12 there is a signal Log. O, then the first

25 shift register, the first and second elements AND, the serially connected element OR, the first and second inputs of which are connected to the outputs of the first and second elements, respectively

which are connected respectively to the output of the subtraction unit and the output of the inverter, and the output of the first switch key 16 is open, and the second switch 17 is closed. The information inputs of the first ZO cops And, and the inverter, the first key, 16, and the second 17 keys are supplied with the same information and control inputs and the same difference signal from the pin of the subtraction unit 6.

Thus, the first key 16 is open only if, when in a difference 35 k ™ second voltmeter,

the second key, the information and control inputs of which are connected respectively to the output of the subtraction unit and the output of the OR element, and the output of the second key is connected to the input of the third voltmeter, the right forward outputs of the second register are connected to the corresponding inputs of the second element, And the inverse outputs of the second the register is connected to the corresponding inputs of the first element And, the output of the subtraction unit is connected to the input of the first volt-n

the signal contains a crushing noise component (), it is measured by a second voltmeter 8 with a quadratic characteristic, and the second key 17 is open only when the overload noise component is present in the difference signal (shown in Figure 2k), which is measured by a third voltmeter 9 with a quadratic characteristic.

40

45

The first voltmeter 7 with a quadratic characteristic allows to measure

total quantization noise power.

meters, D-Trig clock inputs; Gera and the second shift register are connected to the low clock input.

and

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Claims (1)

Claims Noise Measurement Device a delta codec quantization containing a serially connected encoder, a first shift register, a first decoder, an amplifier and a subtractor, a second decoder whose input is connected to a decoder code, and the output is the information input of the delta codec under investigation, the output of which is the second input of the subtraction unit, the first input of the encoder is the information of the ZSNS-1M input of the device, the second the encoder input and the second input of the delta codec under study are respectively high and low clock frequency inputs, characterized in that, in order to increase measurement accuracy, entered the first, second and third voltmeters connected in series threshold unit, the input of which is connected to the output of the subtraction unit, D-flip-flop and the second the shift register, the first and second elements AND, the serially connected element OR, the first and second inputs of which are connected to the outputs of the first and second elements, respectively cops And, and the inverter, the first key, the information and control inputs which are connected respectively to the output of the subtraction unit and the output of the inverter, and the output of the first key of the submente I, and the inverter, the first key, the information and control inputs to ™ second voltmeter, 40 45 meters, D-Trig clock inputs; Gera and the second shift register are connected to the low clock input. pppp nnf g-uj  GShPShShSh1LSHShShPLLShgL1ShLSh1PSh1LShI1LLLLSh1LShShPLPLt Thebes. 2