SU1432461A1 - Programmed control device - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in software control systems and devices that provide control and correction of information received from sensors. The purpose of the invention is to increase the reliability of operation and the range of application. The device contains a control unit 1, first 2, second 3, fourth 4, third 5 memory blocks, first 6 and second 7 analog-to-digital converters (ADC) first- S with tsD O)

Description

output 8, second 9 and third 10 analog to analog converters (D / A converters), first 11 and second 12 input blocks, first 13, second 14, third 15 adders, first 16, second 17, third 18, fourth 19 and fifth 5 registers , direct code to additional converter 21, switch 22, nep-f out 23 and second 24 sensors, first 25 and second 26 control outputs and first 27, second 28, third 29 and fourth 30 synchronization outputs of control unit 1, information output 31 , alarm outputs 32 and errors 33 of the first memory block 2, information output 34, alarm outputs 35 and errors 36 of the second block 3 memories, information output 3 /, alarm outputs 38 and errors 39 of the third memory block 5. The outputs of the first 8, second 9 and third 10 digital-analogue converters are the first, second and third outputs of the device. Such an embodiment of the device for software control allows for elevation; increase the reliability of the operation and expand the scope. 1 hp f-ly, 4 ill.

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The invention relates to automation and computing technology and can be used in systems and software control devices that provide control and correction 5 of information received from parameter sensors.

The purpose of the invention is to increase the reliability of the operation and expand the scope.

Fig. 1 shows a functional diagram of a device for software control with a control; Figures 2 and 3 are functional diagrams of the control and input units, respectively; in fig. 4 - time diagram of the device,.

The device (Fig. 1) contains the control unit 1, the first 2, the second 3, the fourth 4 and the third 5 memory blocks, the first 6 and second 7 analog-to-digital converters (ADC), the first 8, the second 9 and the third 10 digital-to-analog converters (DAC), the first I 1 and BTO- ,, - a swarm of 12 input blocks, the first 13, the second 14 and the third 1 5- accumulators, the first 16, BTOpoii 17, the third 18, the fourth 19 19 and five of the 20 registers, the converter 21 direct code to the additional, switch 22, first 23 and second 24 parameter sensors, first 25 and second 26 control outputs and first 27, second 28, third 29 and fourth 30 out Synchronization odes of the control unit, information output 31, outputs 35 of alarm 32 and errors 33 of the first block

20

thirty

)

,, - 35

0

thirty

2 memories, information output 34, alarm outputs 35 and errors 36 of the second memory block 3, information output 37, alarm outputs 38 and errors 39 of the third memory block 5.

The control unit (FIG. 2) contains a synchronization counter 40, first 41, second 42 and third 43 error counters, alarm register 44, pulse generator 45, start triggers 46 and control 47, decoder 48, first 49, second 50, third 51, fourth 52, fifth 53, sixth 54, seventh 55, eighth 56 and ninth 57 elements AND, element OR 58, first 59, second 60, third 61 elements OR NOT, element 62, toggle switch 63, switch 64, first 65.1 and vtoruk 65.2 buttons and item 66 delay.

Input blocks 11 and 12 contain a resistor 67 and a relay 68.

The control unit is designed to synchronize the operation of the main nodes of the circuit, control the switching of the information transmission circuits of the device, and organize operation control.

The principle of operation of unit 1 is controlled. Nin is as follows.

In the initial state, the memory elements are set to zero. The setting circuits of the initial condition are not shown. By pressing the button 65.1. Starting, the trigger 46 is set to one state and unlocks the pulse generator 45. The pulses from the generator output 45 pulses arrive at

3

the inputs of the element 50 and the decoder 48. If the device operates in the Main operation mode, i.e. implements the control process, the switch 64 is in the initial position and the element And 49 is closed by the left signal. As a result, the elements And 50 and the decoder 48 otkryshayutsya n inverse input. Impulses coming

At the counting input of the counter 40, which, together with the decoder 48, generates four time-shifted pulse sequences (FIG. 4) at the outputs 27-30 of the device.

In this mode, periodically received single signals at the output of the element OR NOT 59 do not block the operation of the element AND 50.

In addition, by pulses from the zero and first outputs of the decoder 48 passing through the element OR 58, the trigger 47 forms the control sinal at output 26 (Fig. 4).

The device is stopped when the Stop 65.2 button is pressed, either by the Alarm signal from the output of the 1-1PI-NE 60 element, or by the signal

error overflow from exit

element OR NOT 61.

The zero-level Avariy signal is generated when one of the triggers of register 44 is set to one at inputs 32.35 and 38. The zero signal Error overflow is due to overflow of one of the counters 41 -43. Counters 41 - 43 performed from the counting of error signals received at the inputs 33.36 and 39 of the control unit 1 through elements 52,54 and 56. The division factor of the counters 41 - 43 is selected on the basis of the allowable number of error signals given out from the outputs 33 , 36 and 39 blocks 2,3 and 5 of memory. With the disappearance of the error signals, the counters 41-43 are reset to the pulses coming from the third output of the decoder 48 through the elements 53, 55 and 57.

In the Control mode, the 1-control unit operates in the same way as described. The difference is as follows. The ler 63 closes and the + power supply is output to the output 25 for switching to the monitoring mode of the input blocks i1 and 12. At the same time, the switch 64 remains in the initial zero state.

d

five

0

five

0

0

with

five

0

five

SRI, if control; -. It takes a cycle for one cycle, or switches to a single state when} 1 control is myocles.

If the switch 64 is connected to the output of the HE element 62, the single signal opens the element AND 49. After pressing the button 65.1, the trigger 46 is set to one, however, the element 49 remains closed at the third input at the time of generation by the generator 45 of the first pulse and the counter is triggered 40 and the element CHI-NOT 59. After the first pulse is recorded in the counter 40, the element AND 49 is closed with a zero signal from the output of the element SHI-NO 59.

Thus, the delay element 66 and the element 49 ensure the resolution of one cycle of operation of the counter 40 in the presence of a single signal at the outputs of the switch 64.

Blocks 2. and 3 of the memory are designed to store information correction codes from sensors 23 and 24. The upper bits of information from the outputs of the A / D converters 6 and 7i are fed to the address inputs of blocks 2 and 3. In accordance with the address, their outputs appear correction codes (outputs 31 and 34), error signals if the code of the sensor outputs goes out of the norm (outputs 33 and 36), and alarm signals if the code from the outputs of the sensors corresponds to an emergency situation (output 32 and 35).

Memory block 4 serves to store the function codes C (1), where 1 | - the corrected sensor code 23 and 24. The memory block 5 implements: storage of control codes issued to the control object in accordance with the address of the error signal and the alarm generated at the outputs 39 and 38.

Memory blocks 2-5 are static-type device ROMs and can be implemented on PT5 chips 556.

A / D converters 6 and 7 are designed to convert analog signals coming from the outputs of blocks 1 and 12 into water into digital codes, and can be implemented on K 1107 IC chips.

D / A converters 8-10 for converting digital codes from outputs of registers 16, 17 and 20 into analog control signals arriving at

Vkody devices can be performed on the chip series K 572.

The input units 1 and 12 switch the analog signals in accordance with the control signals from the control unit 1. In the absence of a high potential at the output 25 of the unit 1, relay 68 (Fig. 3) is de-energized and the analog signal goes through its normally closed contact the output of sensor 23 (34) to the output of block 11 (12) of input (the Main operation mode).

When a high potential is applied to the winding of the relay 68, it triggers and the signal at the output of the input unit 11 (12) is completely determined by the resistance of the resistor 67, which can be changed within wide limits to set the test analog signal of the desired value (Control mode).

The adders 13 and 14 perform the arithmetic summation of the I, and 1 codes coming from the A / D converters 6 and 7 and the I and L correction codes calculated from the memory blocks 2 and 3, respectively, which allows to obtain the corrected values of the codes and I 2k

I h

1 + L I;

 2k

I, + L1,

The need to correct information from sensors can be caused, for example, by nonlinear characteristics of the transfer function Q of the sensor, whose amplitude depends on the size of the input signal,

The adder 15 implements the functions of arithmetic subtraction correlated (the 5th and the transformed code received from the first sensor through blocks 2 and 4 of memory, and from the second sensor through blocks 3 and 4 of memory.

Thus, at the output of the adder 15, a code is generated that is proportional to the value of U

50

And M-d

2k

) H (1 ,,).

Adders 13-15 can be built on the K 155 chips IM 1.

The registers 16–20 are intended for receiving, storing and issuing codes read from memory blocks 2–5 and converted during operation and can be performed on K 155 MI 17 chips.

The converter 21 is used to convert a direct number code into an additional one, which allows an arithmetic subtraction operation to be performed on the adder 15 and is built on the K 115 CL 6 chip.

Switch 22 controls the transfer of information 11, and from the outputs of registers 16 and 17 to the input of memory block 4 in accordance with the control signal from output 26 of block 1.

g g i) kU26Vl2K-U26

g 0

5 o

five

Q

0

6

This device node can be built on the 564 LS 2 chips.

Sensors 23 and 24 serve to convert the measured (monitored) parameter into an electrical analog signal. If such parameters are, for example, static Rst and dynamic pressure, then inductive sensors can be used as sensors.

The device for software control with control works as follows.

Two main modes of operation are possible; the main operation, in which algorithms are implemented for converting information from sensors to control signals (in this mode, operational control of the device and control object is also guessed) and test control, in which various analog signals are fed to test the device.

The operation of the device in the mode of the main operation.

In the initial state, all elements are. memory reset. The initial state setting circuits are not conventionally shown. The switch 64 is connected to the zero pole of the power source, and the toggle switch 63 is in the open state. Input blocks 1 and 12 are configured to transmit information from sensors 23 and 24 (FIG. 3)

After energizing and pressing the Start button 65.1, trigger 46 disables generator 45 (FIGS. 2 and 4). .According to the unsubscribed algorithm at outputs 27-30 sync71432461

The color of control block i appears in a sequence of pulses.

The impulse from output 27 to registers 16 and 7 brings in the corrected information codes from sensors 23 and 24 and ADC 6 and 7 and converted using memory 2 and 3 memories and adders 13 and 14, respectively. Codes I |. and Iji in registers 16 and 17 io are stored for the entire information processing cycle until the next pulse from output 27 of block 1.

These codes, in addition, receive ig on the D / A converters 8 and 9, are converted into control analog signals fed to the outputs of the device.

Trailing edge with zero fC / jtn.

This code is then converted by the D / A converter 10 to an analog signal and fed to the device output.

Then the device operation pkl is lost. If the sensors 23 and 24 generate signals proportional to, for example, static P (.g and dynamic Pq pressures, then memory 4 can realize a logarithmic dependence for these corrected Ig Pj values 2, 3,13,14 . (P), adder 15 allows to obtain a code proportional to

TE

Ig -, and memory block 5 implements

TO

PCT

the functional dependence of the M number and the output of the decoder 48 translates the 2o characterizing ratio of speed into a single state trigger 47 and the object's movement to the speed of sound and generates a single signal at output 26 of block 1. With this signal, the commutator 22 is open to transmit depending on the specified logarithm j to

 ).

M f (lg

formations from register 16,

The impulse from output 28 to register 18 is entered into the code Cfi (I- |,), counted according to the address (code c) from memory block 4.

The falling edge of this pulse; set to zero state trigger 47s which re-arranges switch 22 to transmit information, from register 17.

The next pulse from the output 29 of block 1 to the register 19 is entered the result of information processing from the sensors,

The processing algorithm is as follows. Code 1 in register 18 fixes a code proportional to f (I,), which is then converted to additional code by converter 21. This code arrives on

adder 15, where the object is added (computed-45 control of the object that provides you with the code) with the code Lf (), read from memory block 4 after its address circuits are connected to the register output 17; As a result, the output of the adder 15 is code Lc, equal to the difference of codes

 I.J - (IIK) Lenne emergency situations and repeatedly issued errors, which indicates either a failure of the sensors, or a violation of the process.- control. In the 5Q mode. Test control, the device operation is different in that the toggle switch 63 is closed, the blocks P and 12 inputs connect the outputs of the resistor 67 to supply test analog signals. According to the code u. (F arriving at the address -. 55 If it is required to carry out one cycle

control, the switch 64 is connected to the output HE 62 and unlocked; element 49, thanks to this, when a single signal appears on

the inputs of the memory block 5, the P register 20 according to the sync pulse from the output 30 of the control block 1 is written down

and fC / jtn.

This code is then converted by the D / A converter 10 to an analog signal and fed to the device output.

Then the device operation pkl is lost. If the sensors 23 and 24 generate signals proportional to, for example, static P (.g and dynamic Pq pressures, then memory unit 4 can realize a logarithmic relationship for these corrected at sites 2, 3,13,14 Ig Pj values. ( P), the adder 15 allows to obtain a code proportional to

TE

Ig -, and memory block 5 implements

TO

PCT

the functional dependence of the number M characterizing the ratio of the velocity of the object to the speed of sound and

depending on the specified logarithm j to

 ).

M f (lg

0

This code can then be perceived as controlling actions or as a preliminary result - an information processing for the upper level control device.

The device can be stopped in this mode either when alarm signals appear at one of the outputs 32.35 and 38 of blocks 2.3 and 5, 5 indicating 6

emergency situation by one of the monitored parameters, either by pressing the Stop button 65.2, or by overflowing one of the 41-43 error counters, which indicates that the number of errors was exceeded by one of the parameters.

Thus, in the course of the main operation,

0

the output of the element OR-NOT 59 after the resetting of the counter 40 provides for blocking the supply of pulses from the generator 45. If it is required to carry out a multi-cycle control, the switch 64 remains in the initial position.

In this mode, the external values can be analyzed by external means.

Signal signals of the device, and the input-IQ of the analog-diffractive transducer means using the register 44 and counters 41-43, tested the device for issuing alarms and errors.

Thus, the essence of the invention is to increase the reliability of operation by providing the possibility of periodic test self-control based on the input

control devices, the effects of 2o whose output is connected to the inputs of the first and second blocks that control in a different range of values

fishing and analysis, in the implementation of the built-in hardware control of the device and the object of control on the basis of the boundary values of the localization of emergency situations, as well as in expanding the field of application due to the organization of the preliminary processing of information from sensors and its correction.

Claims (2)

1. Device for software control, containing first and second parameter sensors, first and second analog-to-digital converters, first and second memory blocks, first and second registers, first and second digital-to-analog converters, with the outputs of the first and second digital-to-analog converters are the first and second outputs of the device, characterized in that, in order to increase the reliability of the function and expand the field of application, it further comprises a block, control, the third and fourth memory blocks, the third and fifth registers, the first - the third adders, the code converter, the first and second input blocks, the third digital-to-analog converter and the switch, the outputs of the first and second parameter sensors are connected to the information inputs of the first and second input blocks, respectively, whose outputs are connected to the inputs first and second analog-to-digital converters compliance1; o, the outputs of the first and second analog-digital converters are connected to the first inputs of the first and second adders, respectively, the outputs of which are connected to the HHtbopMaunoHHfcHviK inputs of the first and second registers, respectively., the outputs of the first and second highlights are connected to the inputs of the first and second registers memory blocks, respectively, whose information outputs are connected to the second inputs of the first and second adders, respectively, the first, second and third alarm outputs, and its memory blocks are connected respectively to the first retim inputs of the control unit, the first control input, the second control output is connected to the control input of the switch, the first synchronization output is connected to the synchronization inputs of the first and second registers, the second - fourth synchronization outputs are connected to the synchronization inputs} of the third and third registers, respectively The first and second Istra regs are connected to the first and second digital to analog inputs; 1 of the transducers, the first and second information and 1 input switches, respectively; 5 whose output is connected to the input of the fourth memory block, the output of which is connected to the first input of the total adder and informa -ion:; - the entrance of the third register, whose input is the converter of connection codes with the second inputs of the third summer, the output of which is connected to the information input of the fourth register, the output of the fourth register is connected to the input of the third block gamma t; -, whose information code is connected to the information input of the fifth register, the error outputs of the first, second and third memory blocks are connected to the fourth - six inputs of the control unit, respectively, 3 output of the fifth register through the third n, if the IF converter is connected to the third output of the device, 2. Device, for years. S 5 about tl;: - So, - the control unit contains a synchronization counter, the first - the third error counters, the alarm register, and an img pulse generator. Triggers start and control, decoder, the first - the ninth elements AND, the element OR, the first - the third element OR-NOT, the element NOT, the toggle switch, the switch, the first and second buttons, the delay element, and the bus positive potential of the power source through the toggle switch is connected to the first the control unit's output, -JQ input of the decoder, the third input is the first - the third inputs of which of the connecting element I are delayed through the element with the first - the third inputs of the alarm register, respectively, the zero potential potential of the power supply ki is connected to the trigger trigger output, the first and second decoder outputs are connected to the first one, respectively. connected to the normally closed and 15 and the second inputs of the OR element, through the NOT element with the normally open circuit of which is connected to the counting input contacts of the switch, the output of the control trigger, the output of which is connected to the first input of the first element the output of the first element is the second control output of the control unit, the first is the third and is connected to the inverse control input of the decoder and the inverse input of the second element I, the output of which is connected to the counting input of the synchronization counter, bus zero second power source potential through the first and second buttons respectively connected with the input unit trig ger start and the first input of the third AND gate, whose output is connected with zero start trigger input, error through the third element OR — NOT the synchronization counter moves are connected to the third input of Fretoe with the information inputs of the decoder, the element I, and the fourth output of the decoder is the first to fourth outputs of the torus connected to the second inputs Thu- are the first - the fourth output of the - the nine elements I. Synchronization of the control unit, respectively, the outputs of the synchronization counter through the first element OR-NOT is connected to the second input of the first element AND, the output of the start trigger is connected to the input of the generator, the output of which is connected to the direct input of the second element AND and the forward control the input of the decoder, the third input of the first element And through the element of the delay ki is connected to the trigger trigger output, the first and second decoder outputs are connected to the first one, respectively. and the second inputs of the OR element, the output of which is connected to the counting input of the control trigger, the output of which is the second control output of the control unit, the first - the third outputs of the alarm register are connected through the second OR element to the second input of the third And element, the i-th input of the control unit (i 4,5,6) is connected to the first input of the g- th and inverse input (g + 1) -th elements And (), the outputs of which are connected to the counting and installation inputs j-ro error counter (J 1 i-3), respectively, the outputs of the first - third counters K68  Rig.Z