SU1425868A1 - Receiver of phase/frequency-manipulated signals - Google Patents

Abstract

The invention relates to radio engineering and can be used in radio engineering systems for the transmission of discrete information. The purpose of the invention is to increase the noise immunity of the reception of phase-shifted signals. The receiver of the phase-frequency-manipulated signals contains a frequency detector 1, a delay line 2, integrators 3, 8, a carrier batch 4, a phase detector 5, ADC 6, 12, key block 11, a frequency generator 14. The goal is achieved by introducing into the device a code 15 generator, a register 16, a key block 17, a block of phase shifters 7, a serially connected discrete matching filter 9 and a block 10 of control, a block of adders 13. 2 Il.

Description

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The invention relates to radio engineering and can be used in radio engineering systems for the transmission of discrete information.

The purpose of the invention is to improve the noise immunity of reception of phase-shift keyed signals.

FIG. Figure 1 shows the structural electrical circuit of the proposed receiver; 2 is a control unit.

The receiver of the phase-frequency-manipulated signals (Fig. 1) contains a frequency detector 1, a delay line 2, a first integrator 3, a carrier unit A, a phase detector 5, a first-: analog-to-digital converter 6, a unit 7 of phase shifters, second integrator 8, discrete matched filter 9, control block 10, first key block 11, second analog-to-digital converter 12, block 13 adder, frequency generator 14, code generator 15, register 16, second key block 17.

The control unit 10 (FIG. 2) contains decoders 18 and 19, gates 20 and 21, triggers 22 and 23.

The receiver works as follows.

The phase-frequency-manipulated (FFM) signal arrives at the receiver input, which can be represented as

S (t) A sin S aw (t) dt-i-fly (t)

where A is the amplitude of the signal envelope

.

and / 0 the circular frequency and the initial I on the phase of the carrier oscillation iuj (t) - the law of changing the frequency

real fluctuations; (t) is the law of change of the signal phase.

From the receiver input (Fig. 1), the signal is fed to the input of the frequency detector 1 and the delay line 2. At the output of frequency detector 1, a voltage is generated, which is a function of the declination of the frequency of the received signal element, i.e. signal taken per clock interval, f..OT of frequency tuning frequency detector 1 f:

Uoo (f (. - f). This voltage is integrated over the time of the clock by the first integrator 3, the transfer function of which is determined by

with

0

5 0 5

0

five

0

5 gp

five

and V 5 and, (t) dt,

about

where is the integration time constant.

The voltage from the output of the first integrator 3 is fed to the input of the first analog-to-digital converter (ADC) 6, which converts this voltage into a sequence of binary signals (code) corresponding to the frequency of the received signal element. This code is fed to the output of the frequency sub-channel of the receiver.

Line 2 delays produces for -, -. .. holding the FMFM signal for a time tj equal to the duration of the processing of a signal element in the frequency subchannel (per clock cycle). The signal delayed by time tj is fed to the input of the carrier extraction unit 4, in which the coherent adjustment of the internal reference oscillator is performed according to the received signal and the allocation of the carrier wave. This reference oscillation is fed to the block 7 of phase shifters, which produces a phase shift of this oscillation by O, / 2 2ir / 2-4.,., () I7 / 2 -V. The reference oscillations with these phase shifts from the corresponding outputs of the block 7 phase shifters are fed to the signal inputs of the second key block 7s- which connects one of its inputs to the output in accordance with the control signal.

This control signal is generated by the control unit 10 on the basis of an analysis of the error code received from the outputs of the block 13 of adders. This code is the sum modulo 2N-size of the day sequence coming from the outputs of the register 16 and the N-bit sequence that is a copy transmitted sync sequence and coming from the outputs of the generator 15 code. This copy of the sync sequence also goes to the matching inputs of the discrete matched filter 9, which forms the signal of a logical unit if the sequences received at its input and to the matching inputs are the same. The appearance at the output of a discrete matched filter .9 signal of a logical unit in the case if the sequences arriving at its input and at

matching inputs are the same, means receiving the transmitted sync sequence through the frequency channel. At this moment, the signals at the outputs of the block 13 of adders correspond to the indicated error code, which is fed to the inputs of the decoders 18 and 19 of the block 10 of the control.

Each mismatch code corresponds to a certain phase shift that occurred in the carrier separation unit 4 in the event of the indicated interfering factors. In accordance with a certain type of mismatch code, a single signal passed through the corresponding valves 20 and .21 from the output of one of the triggers 22 or 23 of the block 10 control is fed to the control inputs of the second key block 17, connecting to the output of its input, the Tolya which maintains the corresponding equality, i.e. the output of the phase shifter unit 7, in which the random phase shift of the reference oscillation is compensated by the corresponding phase shifter. In this case, to determine the sync sequence code equivalent to the specific phase shift, the length of the sync sequence N is chosen from the condition Ni. 2 ,.

The reference oscillation with the corrected phase from the output of the second key block 17 is fed to the input of a frequency generator 14, which forms a grid of reference frequencies. One of the reference frequencies in accordance with the code of a certain frequency of the received element of the signal that is sent to the control input

of the first key block 11, is connected to its output and is fed to the second input of the phase detector 5. At the output of the latter, a voltage is generated, which is a function of the phase difference of the received and reference signals:

Upc (on)

This voltage is allocated by the second Integrator 8 and is fed to the input of the second ADC 12, which is converted

five

0

0

five

0

five

breaks it into a code corresponding to the phase of the received signal.

Claims (1)

Invention Formula Receiver of phase-frequency-manipulated signals containing a frequency detector connected in series, the first integrator, the first analog-digital converter and the first key unit, to the signal inputs of which are connected the frequency generator outputs, successively connected delay lines, the input of which is connected to the input of the frequency detector , phase detector, to the reference one. the output of the first key block, the second integrator and the second analog-to-digital converter and the carrier extraction unit are connected, to the input to Secondly, the output of the delay line is connected, characterized in that, in order to increase the noise immunity of receiving the phase-shift signals, a code generator, a register, a block of adders, a second key block, a block of phase shifters and a serially connected discrete matched filter and a control block whose outputs are connected are kept to the control inputs of the second key block, the signal inputs and the output of which are connected respectively to the outputs of the block of phase shifters, to the input of which the output of the allocation unit is connected it, and with the input of the frequency generator, while the code generator outputs are connected to the matching inputs of a discrete matched filter, the signal input of which is connected to the output of the first analog-digital converter, and to the single inputs of the block of adders, the other inputs and outputs of which are connected respectively to the outputs register - pa to the input of which the output of the second analog-to-digital converter is connected, and with the signal inputs of the control unit. C4J