SU1418723A1 - Buffer memory device - Google Patents

Abstract

This invention relates to digital computing. The purpose of the invention is to reduce hardware costs. The device contains counters 1 and 2 addresses, blocks 3 and 4 of memory, delay element 5, pulse generator 6, input 7, trigger 8, AND 9-12 elements, OR elements 13 and 14, And 15 and 16 elements, elements 17 and 18 delays. The single position of the trigger 8 corresponds to the mode for block 3 and the read mode for block 4, and the zero position of the trigger 8 corresponds to the write mode for block 4 and the read mode for block 3. In the write mode, frequency pulses from the generator 6 are sent for block 3 through the released element 9, and for block 4, respectively through element 12. In this case, the write command for each memory block is divided into two channels; control on the write-read input and on the input of the chip selection on the block of block 3, the write command in the form of the write frequency pulse passes through the elements 17 and 18o; moreover, the element 18 operates in two blocks, and its response time is longer with respect to the elements 17 and 5. control delay on input is provided. Choice of crystal in both blocks with respect to input Y

Description

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the bath at the time of arrival of the recording frequency pulses. At the end of the recording frequency pulse, the AND 9 element closes and the element 17 starts to operate, the response time of which is equal to the response time of the AND 15 and OR 13 elements. Thus, the disappearance of the control signals for the Record-read and Select inputs

Kristashsh occurs simultaneously. In the read mode for block 3, read pulses from another output of generator 6 pass through the open element 11 and through the OR element 13. input Select the crystal of block 3. In the same way, block 4 operates in the write or read modes. 1 Il.

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The invention relates to digital computing, in particular to devices for interfacing with memory, and can be used to build systems with high-speed memory.

The purpose of the invention is to reduce hardware costs by simplifying the data acquisition algorithm,

The drawing shows a block diagram of the proposed device.

The device contains counters 1 and

2 addresses, blocks 3 and 4 of memory, element

5 delays, generator 6 pulses, device start 7 input, trigger 8, elements AND 9-12, elements OR 13 and 14 elements AND 15 and 16, elements 17 and 18 delay

The device works as follows.

The information to be recorded at input and 1 in blocks 3 and 4 is associated with the trigger signal at input 7 and, if necessary, can be synchronized with recording frequency pulses from the first output of generator 6 (not shown).

The trigger signal at input 7 is also used for synchronizing counters 1 and 2,

Information read from blocks

3 and 4 can be combined into one channel through an OR element and, if necessary, synchronized by read frequency pulses with a delay for the response time of blocks 3 and 4, for this purpose a careful multivibrator triggered by pulses can be used

Synchronization of input and output information can be implemented on triggers.

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ABOUT

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The single trigger output 8 corresponds to the write mode for block 3 and the read mode for block 4, and the zero output of the trigger 8 corresponds to the read mode for block 3 and the write mode for block 4,

In the information recording mode for blocks 3 and 4, the write frequency pulses from oscillator 6 are received through the open elements AND 9 and 12, respectively. At the same time, the write command for each memory block is divided into two channels: input control Write-read and chip select input. For block 3, the write command in the form of a pulsed write frequency passes through elements 17 and 18, and the response time of element 18 is faster than the response time of element 17, thereby providing an input control delay. Choosing a chip with respect to the input Record-reading at the time of arrival of a frequency pulse recording from the generator output 6, At the end of the pulse frequency of the recording element (And 9 closes and the element 17 starts to operate, the response time of which is equal to the response time of the elements And 15 and OR 1 3, thus disappearing si catch control inputs of recording and reading-crystal Selection occurs simultaneously,

In the read mode for block 3, the coupling frequency pulses from another output of generator 6 pass through the open element 11 and through the element OR 13 to the input of the selection of the crystal of block 3.

Similarly, the block 4 "operates in the write or read mode.

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If information on the distortion of the reliability of information from the control unit is received in the work flow, then this signal can be used to convert blocks 3 or 4 to work on the reserve zone, which is connected to the work by changing the potential at the input of the higher address bit,

The change of the memory address in blocks 3 and 4 occurs by a decrease in the pulses at the inputs. The choice of a chip, which from elements 13 and 14 enters the corresponding counters 1 and 2, both in the write mode and in the read mode.

Claims (1)

Invention Formula A buffer memory device containing two address counters, two memory blocks, a trigger, six AND elements, two OR elements, a trigger synchronization input is a device start input and is connected to the reset inputs of the first and second address counters, the outputs of the first and second address counters connected to the inputs of the lower bits of the address of the first and second memory blocks, respectively, the direct output of the trigger is connected to the first inputs of the first and second elements And, the inverse output of the trigger is connected to the first inputs of the third and fourth e The elements And, the outputs of the first and fourth elements And connected to the first inputs of the fifth and sixth elements And, respectively, the outputs of the fifth and sixth elements And connected five 8723 with the first notes of the first and second elements OR, respectively, the outputs of the third and second elements And are connected to the second inputs of the first and second elements SH, respectively, the output of the first element OR is connected to the input of the Sampling chip of the first memory block and the counting input of the first Q address counter, the output of the second the OR element is connected to the Sampling input of the second memory block and the counting input of the second address counter, the information inputs of the first and second memory blocks are the first and second information inputs of the device. Arrangements, the outputs of the memory blocks form the information output of the device, characterized in that, in order to reduce hardware costs, three delay elements and a pulse generator are introduced into it, the first frequency output of the pulse generator is combined with the second inputs of the first and fourth elements And, and through the first the delay element is with the second inputs of the fifth and sixth elements And, the second output of the pulse generator is connected to the second inputs of the second and third elements And, the output of the first element And is connected through the second delay element to the input ch audio-write the first block of memory, the fourth output element and is connected via a third delay element to the input of the read-write memory of the second unit, the inputs high bits of addresses of the first and second memory blocks are inputs reservation memory device units. 0 five 0 five