SU1415382A1 - Device for controlling d.c. to variable three-phase voltage converter - Google Patents

Abstract

The invention relates to converter technology and can be used in the construction of secondary power sources of both centralized and decentralized type in all cases when, according to the operating conditions, improved weight and dimensions of the device and improved quality of the converted electric power with adjustable parameters are required. The purpose of the invention is to improve the quality of the output voltage and increase efficiency. The device provides control of a constant-voltage converter B, an adjustable three-phase one. Voltage regulation is performed by the partial pulse-width regulation method without the inherent complication of the known power section of the converter. Device for up; The converter contains two frequency dividers, a six-hub pulse distributor, two 1K-triggers, an auxiliary logic node and two main logic nodes, the outputs of which are connected to the control inputs of the power switches of the converter, two elements 2 OR, and two logical elements NOT. 4 il. § (L

Description

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00

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The invention relates to a conversion technique and can be used in constructing sources of secondary power supply of both centralized and decentralized types in all those cases when improved weight and size parameters and increased quality of converted electricity are required.

The purpose of the invention is to improve the quality of the output voltage of the converter during its regulation and increase the efficiency by reducing the number of switches of its keys per unit of time,

Fig. 1 is a diagram of the proposed device for controlling the converter; Fig. 2 shows timing diagrams for explaining the principle of generating control signals by converter keys; FIG. 3 is a schematic diagram of the power section of the converter, for whose controls the proposed device is applied; Fig. 4 shows timing diagrams for explaining the principle of formation of the output phase voltage on the load with a single value of the control angle O (e O,

A device for controlling a constant-voltage adjustable three-phase converter (the power part of which is shown in FIG. 3) includes a frequency adjuster 1 connected to the first 2 and second 3 frequency dividers, the outputs of which are connected to the inputs of element 2-HE 4 Output the latter is connected to the input of a six-channel distributor of 5 pulses, made of six IK-triggers 6-11. The outputs of the first 2 and second 3 frequency dividers are also connected to the inputs of logic element 2ILI 12, in addition, the output of the second frequency divider 3 is connected to the counting input of the first 1K trigger 13 and to the clock input of the pulse width modulator 14. The output of logic element 2 OR 12 is connected to the counting input of the second 1K-flip-flop 15, the setup input I of which is combined with the installation input 1 of the first 1K-flip-flop 13 and connected to the output of the logic element 2I-HE 4. The inverse output of the second 1K-flip - Hera 15 Qn is connected to one of the inputs of the second logical element OR 16, the other input of which is connected

with y

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20 5 30

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Yen with the modulator output 14 of the pulse width S, the device for controlling the converter also includes three logical nodes: an additional 17 and two main 18 and 19, which generate the control signals by the keys of the converter.

Additional logic node 17 contains two channels, the first includes the first logical element NOT 20 the logical element 2I-2ILI 21 and the second logical element NOT 22, Communication between the outputs Q and Q of the first 1K-trigger 13, the output S of the modulator 14 pulse width, output Q | the second 1K flip-flop 15, the input of the first channel of the additional logical node 17 and its output F are determined by the following logical expression:

F (Q, + S) QT + (QJ -t- S) QT.

The second logic element NOT 22 inverts this signal. The second channel of the additional logical node 17 also contains the logical elements NOT 23 and 2-2ILI 24, Communication between the inputs of these elements 23 and 24 with the outputs of some of the listed nodes and elements (13 and 14) with the output H of the second channel

the additional logic node 17 is determined by the logical expression

H + Q7S.

The outputs F, F, H of the additional logic node 17 are connected to the inputs of the first main logic node 18, the other inputs of which are connected to the paraphase outputs Q, Q - Q j, Qj of the first half of 1K-flip-flops 6-8 two-five-channel distributor 5 pulses and outputs Q7, QT of the first 1K flip-flop 13.

Logic node 18 is made in the form of three identical channels, each of which contains four logical elements ZI 25-36, logical element 4 OR 37-39, and logical element NOT 40-42. At the output of the logical element ZI 25, a signal is formed and the logical expression is ,, siotvetstneino on a voyage; lo; -ich (-. scs: th element 311 26 - rbQ: ili, 27 - qiQ-r, 28

Q, Q.F. The output of the logic element 4 OR 37 form a logical signal Ml (one of the output signals of the device), equal to M1 Q Q Q + -t- +, and ia the output of the logic element HE 40 is the signal Ml. The remaining channels are similarly similar, so that at the output of logic element 4 OR 38 a signal M, QjQjQ, + Q, Q, H + 4 Q is formed. Logical element 4 OR 39 - Mj Q, QjQjH -j QjQgF-Q QjQjF. The outputs of the logical elements of HE 41 form -signal M-, 42-M ,. The outputs M, M, - M, M form one output group of the device for controlling the converter (Fig. 2) associated with the control inputs of the modulator keys. The same group of outputs includes outputs Q-, Q of the first IK trigger: M T)., M Q. The second main logic node 19 is also made three-channel. The structure of each channel includes a serially-connected logical element 2-2 and -OR 43-45 and a logical element NOT 46-48. The connections from output # 1 Q, Q - Q ,, Q of the trigger 9-11 of the distributor 5 pulses and Q- ,, QJ of the first 1K-trigger 13, are made to ensure the implementation of the following logic functions: at the output of the spindle element 2-2I- OR 43 DM, 4+ q-, Q4, 44 DM + Q-, Q. 45 DM- Q, Q +. At the output of the logic element, HE 46 form the signal DM, 47 DM, 48 DMJ, respectively. These outputs form the second group of outputs associated with the control input of the demodulator keys. The power part of the converter (Fig. 3) contains a modulator 49, retained in the form of four racks of switches 50-57 (in Fig. 3, for example, in the form of a transistor, shunted by a reverse current diode) with control inputs Mi,, M. the middle points of the racks of the keys 50-57 are connected to one ends of the primary windings 58-60 of three single-phase transformers 61-63, the second ends of which are combined and connected to the middle point of the keys 56 and 57 of the fourth rack. The secondary windings 64-66 are connected to three single-phase demodulators 67-69. Demodulators 67-69 can be made using any single-phase scheme (for example, single-phase pavement) to the floor

five

five

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five

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nostaty controlled AC clips. On (ig.Z demodulators 67-69 are made according to the scheme with a zero point, on the keys with control inputs DM, DM, - DM2, C (. The secondary windings 65-66 in this case have a midpoint, which is one of Vygodov demodulators 67-69 (united in a common point). Other outputs of demodulators 67-69 form output outputs 76-78 (A, B, C) of the converter. Outputs M, M - Mj, Mj of the first logical node 19, M, M of the first 1K-flip-flop 13 is connected via an amplifier-decoupling node with the corresponding control inputs of the keys of the motor / tulator 49, and the findings of the DM,., DM-of the second basis logical gate 19 - with control inputs, a switch of 70-75 demodulators 67-69.

The principle of operation of the device for controlling the converter is explained in the time diagrams presented in Fig. 2. Frequency reference 1 synchronizes the operation of the device. The pulses of the form and from its output arrive at the inputs of dividers 2 and 3 frequencies, the division factors of which are defined as N and N + 1. It is in this case that a sequence of pulses 1) 4 is formed in the 2I-NO 4 comparison circuit (the frequency of which is 12 where f g is the frequency of the output voltage of the converter), which is fed to the input of the distributor – i 5 pulses. The latter with the help of triggers 6-8 ensures the formation of three sequences of paraphase pulses Q,, Q with a frequency of 2 fji ,,, shifted by an angle of / 3, and with the aid of triggers 9-11 - three sequences of paraphase pulses Q, Q - Q , Q, having frequency f ,,. and a phase shift of 2TG / 3 angle.

Dividers 2 and 3 frequencies are formed by forming a sequence of narrow pulses (Uj, and). After logical addition of these pulses using logic element 2 OR 12, the sequence of pulses U is fed to the input of the 1K flip-flop 15. To eliminate the ambiguity state and thereby increase the functional reliability of the device as a whole, a sequence of narrow pulses is applied to the set I input of the flip-flop 15

at the output of the trigger 15. a sequence of pulses of the form U. modulated by duration will be formed. It is fed to the input of the second logic element 2I16, the second input of which receives a sequence of pulses S from the output of the pulse width modulator 14. The modulator 14 provides, in accordance with the signal Ug (the formation of a sequence of pulses Uf4, the duty cycle of which varies from 0 to 1. Logical nodes 17-19 are implemented on standard microcircuits ensuring the implementation of the known logic operations. The signals and outputs of some of them are shown in Fig. 2 FIoMepa signal sequences correspond to the chip numbers.

A feature of the modulator 49 is the use of a common rack of keys 56 and 57 for forming modulated voltages 61-63 of all three phases of the converter. The control inputs M, M of these keys give a signal Q, Q from the output of flip-flop 13, which ensures switching these keys with constant frequency. The control inputs M, M - M, M of the remaining switches 50-55 of the modulator 49 provide control signals with a greater or equal frequency at control angles O, or a signal of equal frequency and a variable duty cycle signal of type U, .U (type F , H) (UjT - Ujj in FIG. 2) at (/ e O at the respective conduction intervals due to the required phase shift of the control signals. Having the same switching frequency of the keys 50-55 and 56, 57 of the modulator 49 allows forming the windings transformers 61-63 variable high-voltage rectangular shape s (for example, in the interval - 12 in Fig. 4), the introduction of an adjusting pause of duration oi into the control signal and the same keys in the conduction interval / 2-511/6 ensures the formation of the corresponding signal (Fig. 4). The difference in the switching frequency keys 50-55 of the switching frequency of the keys 56 and 57 allows you to generate a variable modulated voltage at about 0, or the voltage of the form Ufo on the interface 53826

shafts - G / b and - Tf / 6. This form of voltage allows to obtain at the inputs of three modulators, the keys of which switch with a constant frequency, but with a change in the order of phase alternation through the half-period of the output frequency (U, - .. in Fig. 2), the phase voltage prevailing the developer of the form U or linear (figure 4).

By comparing the number of switchings of the power switches 50-57 and 70-75 of the converter controlled from the proposed device with the number of switches of the same keys in the known device, it can be shown that in the keys of the modulator 49, it increases approximately 1.5 times on the other hand, in modulators is reduced by a factor of 2. The dynamic losses in the transistor switches of the converter devices are substantially dependent on the switching voltage. Usually converters

5 of this type for converting a constant voltage of 27 V to a voltage of about 200-220 V, i.e. demodulator keys operate at an increased voltage that determines

0 and a higher level of dynamic loss. Thus, although the number of switches of the modulator has increased, with the indicated ratios of input and output voltages, the total dynamic losses decrease by about 1.6 times, and the efficiency of the converter will increase by 5-8Z.

The proposed output voltage regulation algorithm allows

0 also improve its quality. The adjustment range is 1-0.57. At the same time, for the case (/ s / "c, cc, when i. 0.57 Ug ,,", K g (", 0.31. For the same value of the output

{the voltage in the known device is approximately 1, G2, i.e. worse than the proposed 3.6 times.

The proposed device for controlling the converter can find

application in the construction of centralized power sources, when it is required to provide as an agreement the nominal voltage levels

g power and load, so. and stabilization of the surge voltage when the supply voltage varies within fairly wide limits (± 20%) with high quality output voltage and power

71

Geometric conversion rates.

Claims (1)

Invention Formula A device for controlling a constant-voltage three-phase adjustable voltage converter, including a modulator in the form of four key racks with control inputs M, M - M, M connected between the supply voltage, three single-phase transformers, one of the primary windings of which are connected respectively to the points of connection of the keys of the first three racks, their other ends are combined and connected to the point of connection of the keys of the fourth rack, and three single-phase demodulators on the AC switches with the control inputs DM, DM, DM connected to the secondary windings of the corresponding transformers, and one demodulator terminals of the same name are combined, while others form the output terminals of the converter containing two frequency dividers connected by inputs to the output of the frequency adjuster, and outputs to the logic element 2I-HE, the output of the latter is connected with a counting input of a six-channel pulse distributor made on six 1K-triggers with cross-links in one half of the triggers, and the paraphase outputs Q, Q - Q /, Q. of these triggers are connected to the corresponding three main outputs M M - Mj, Mj of the first one and three pairs of outputs DM,}, DM, - DM, DM2 of the second are connected to the control inputs of the modulator and demodulator keys, respectively, as well as the first 1K-three ger with paraphase input Q, Q ,, associated with the control inputs of the keys of the fourth rack of the modulator. So that M Q, Mc Q, and secondly 1K-trigger with output Q., pulse width modulator , the clock input associated with the countable input of the first 1K-flip-flop, the output S with the first input of an additional logical node, including matching logic gates, and two logic gates 2 OR with outputs F, H, the other inputs of which are connected to outputs Q, Q of the first 1K-flip-flop and connected to output Q of the second ten 15 20 53828 The 1K flip-flop, the connections between the S and Q, Q outputs of the pulse width modulator and the first 1K flip-flop and the H output, are determined by the logical expression H-b, the indicated outputs F, H and the Q, Q- outputs, the first 1K -trigger is connected to the remaining inputs of the first and second main logic nodes, the setup input J of the first 1K-flip-flop is connected to the output of the said logic element 2I-NOT, and its counting input is connected to the output of the second frequency divider, which differs in that in order to improve the quality of the output voltage and increase the efficiency by reducing the number of switches of its keys per unit of time, it is equipped with two logical elements ORI and two logical elements NOT, the second half of the 1K-flip-flops of the above-mentioned six-channel distributor of pulses 25 is cross-linked, and their counting inputs are connected to the corresponding outputs of the first half 1K-flip-flops, the counting inputs of the latter are connected to the output of the logic element 2I-NOT directly, the connection between the above-mentioned logic elements, pulse distributor, mod l torus pulse width, first and second flip-flops-1K, an additional logical node and the output device through the first and second logical nodes, and the implementation of these logical nodes are determined sledujushchi Q E E logical expressions: F (QJ + S) QT + (Q + S) m, .qt + + 45+ + QiQjF; M i QiQjQT QiQiK + + + Q, Mj Q, Q, QT + QiQ, H + 4- QiQjF + QiQjF; 55 QiQ Q-rQf; DM1 Q-rQt + DMZ + Q-Ps thirty 35 50 /// L / h 17 T1 .J .l AP ./7j i - -tf /%. u Ttg