SU1413615A2 - Basic function generator - Google Patents

Abstract

The invention relates to computing and can be used to generate basic functions, for example, in the spectral analysis of random processes. The purpose of the invention is to expand the functionality by generating basic functions, taking into account the sign of a zalon. The goal is achieved by introducing N / 2 one-bit adders. The functional converter additionally includes the first and second decoders, the memory unit, and the switch. 1 hp f-ly, 2 ill.

Description

with

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The invention relates to computing and can be used to generate basic functions, for example, in the spectral analysis of random processes.

The purpose of the invention is to expand the functionality by generating basic functions taking into account the sign of the standard and increasing the reliability of the result by eliminating uncertainties of the x / o and o / o types.

FIG. 1 shows a structural diagram of the generator in FIG. 2 is a diagram of a functional converter.

The basic function generator (GBF) contains (figure 1) input registers 1-8, one-bit adders 9-1 quadrants 13-20, functional converters (FP) 21-27p, output registers 28-34, pulse generator 35 ), the counter 36, the decoder 37 and the trigger 38. The OP (FIG. 2) contains an adder 39, a divider 40, a sine (cosine) square calculation unit 41, a square root extraction unit 42, decoders 43 and 44, a memory block 45 and a switch 46.

The generator works as follows.

GBF works like a prototype device. Before the operation of the device, the GI 35 is turned off, the counter 36 and the trigger 38 are set to their initial, for example, zero state. When the start-up device arrives at the start input, the start-up pulse 35 is inserted, and the signal standard is written to registers 1-8 from the reference vector reference inputs. The frequency of the pulses at the output of the GI 35 and the capacity of the counter 36 are chosen so that the formation time at the input of the decoder, 37, of a certain code combination is equal to the time of conversion of the standard into the coefficients of the basic system of functions.

Reference samples from the outputs of registers 1–8 are fed through quadrants 13–20 to the inputs of the FP 21–27. The inputs of the FP 22 are fed to the outputs of the quadrants 15 and 16, to the inputs of the FP 21 from the outputs of the quadrants 13 and 14, to the inputs of the FP 23 - from the outputs of the quadrants 17 and 18, to the inputs of the OP 24 - from the outputs of the quadrants 19 and

At the first outputs of the FP 21 - 27, the sine and cosine codes of the desired basic system of functions are formed. H

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five

0 5

five

0

five

0

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the second outputs of the OP 21-24 are formed, respectively, the sums of squares of the samples X - C, C. XI, X2, C + X1. These sums are applied respectively to the first and second inputs of the FP 25, to the first and second inputs of the FP 26.

At the second outputs of the OP 25 and 26, respectively, the sums of squares of the samples X2 + C + C + C and C + X | -i X | are formed. These sums are fed to the first and second inputs of the FP 27. At the end of the work of the FP 27, the input of the output registers 28-34 is sent to the pulse from the decoder 37 and the resulting sine and cosine values of the basis are written to the output registers 28-34. Simultaneously trigger 38 is set to the state informing that the formation of the basic system of functions has been completed.

The formation of basic functions taking into account the sign of the standard is provided by single-digit adders 9-12, the inputs of which are supplied with the potentials of sign bits from the sign outputs of the input registers 1-8. The potentials of the sign bits are respectively supplied from the first and second inputs of the registers 1 and 2, to the first and second inputs of the adder 10, from the sign outputs of the input registers 3 and 4, to the first and second inputs of the adder 11, from the sign outputs of the input registers 5 and 6; to the first and second inputs of the adder 12 - from the sign outputs of the input registers 7 and 8. The result of adding modulo 2 (,,) is fed from the outputs of the adders 9 to 12 to the sine sign inputs, respectively, output registers 28, 30, 32 and 34, which are the PSI .1us codes of sines (cosine of the r. jyu Hood matrix. The core of the third Hood matrix depends on the sign of the eta samples.

The principle of operation of OP 21 - 27 is as follows. Input data, such as X and X, is fed to the first and second inputs of the adder 39 and the divider 40. The sum X + X from the output of the adder is fed to the second output of the AF. At the output of the divider 40, an X / X type ratio is formed, according to which, at node 41, the values,, and are calculated. The latter are transmitted through node 42 to the first input of switch 46, which in its initial state

3,

provides connection of the output of node 42 to the first output of the OP.

. If the first and / or second input of the FP is given a zero value, then the corresponding decoder is triggered. Switch 46 connects to the output of the FP via the second information input the code of memory block 45. The latter contains sine and cosine codes, for example, O and 90. When X, O, the second information input of the switch 46 is supplied with a sine (cosine) 0 ° code, with X (equal to some number or O, and X O, the second information input of the switch 46 is fed with a sine (cosine) code 90 °.

Claims (1)

1. The generator of basic functions on the author. St. No. 1319013, characterized in that, in order to extend the functionality by generating basic functions taking into account the sign of the standard, N / 2 one-bit adders are entered into it, with the first and second inputs i-ro (i 1, N / 2) one-bit This adder is connected to the sign outputs 2i-T-ro and 2i-ro input registers, respectively, the output of the i-ro adder is connected to the sign input of the output to 15 3615 register connected to the i-th function of the converter of the first group. 2, The generator of claim 1, in order to increase the reliability of the result by eliminating ambiguities such as x / o and o / o, the functional converter contains an adder, a divider, a node for calculating the square of syn, nusa ( cosine), square root extraction node, two decoders, a memory unit and a switch, the first and second inputs of the functional converter are connected to the first and second inputs of the divider and adder and the inputs of the first and second decoders, the output of the divider is connected to the input of the calculation node square the sine costa (cosine), the output of which is connected to the input of the square root extraction node, the output of which is connected to the first information input of the switch, the second information input of which is connected to the output of the memory unit, the first and second address inputs of which and the control input of the switch connected to the outputs of the first and second decoders, the outputs of the switch and the adder are connected to the first and second outputs of the functional converter. 0 0 e) (odes tasks of the benchmark boho run epi / ncpt cut 39 kO fiJ kl Ml. h5 if6 FIG. 2