SU1406567A1 - Program control device - Google Patents

Abstract

The invention relates to an automatic control technique and can be used to control equipment according to a cyclic program. The aim of the invention is to increase reliability by simplifying the device, increasing its noise immunity and ensuring prompt correction of time lag values. The device for software control contains an input unit, which can be used as a multiplexer, two serially connected counters, the counting input of the first counter is connected to the output of the pulse generator, and the reset input is connected to the output of the input block, the outputs of the second counter are connected to the address inputs of the memory block These, the first outputs of which are the command outputs of the device, the second outputs determine the transition conditions and are connected to the second inputs of the input block, and the third outputs specify the control code tim frequency pulse generator. In order to reduce the equipment, the second inputs of the input unit can be connected to the outputs of the second counter, and 1 Cp. f-ly, 3 ill. i (L

Description

This invention relates to automatic control and can be used to control equipment according to a cyclic program.

The aim of the invention is to increase reliability by simplifying the device, increasing its resistance to life and providing the possibility of promptly adjusting time-delay values.

Fig. 1 shows a functional diagram of the setup 5 (Functions} in Fig. 2 is a variant of the expanded circuit of the device; Fig. 3 is a syringe diagram of a pulse generator with control outputs of a decoder frequency.

The device contains an input unit 1, the first inputs 2 of which are connected to the inputs of the device, a generator of 3 pulses, the first and second counters 4 and 5, the block 6 of memory, the outputs 7 of which are connected to the outputs of the device. In addition, there are multiplexer 8, transistors 95 10, capacitors 11 and 12, resistances 13-15, variable resistances 16.1-16.p.

The device works as follows.

When turning on the dongle, counters 4 and 5 are nullified. At the same time, at the output of counter 5, the code of the first address is generated arriving at the address input of memory block 6. At the output 7 of the device, the code of the first operation is formed, and the input of the control of the generator of 3 pulses receives the code of the first time interval, which determines the generation frequency. Counter 4 is reset to zero, since a zeroing signal from the output of input block 1 is present at its reset input.

When applied to the input 2 devices.; the input signal and the control input of the input block 1 of the signal from the memory block 6, the input block 1 removes the zero signal from the reset input of counter 4, which starts counting pulses arriving at its counting input from the generator 3. The time of filling the counter is determined generator frequency 3 controlled by the code of the first time interval from the output of memory block 6. After filling the counter 4, the counting input of the counter 5 receives a signal, which forms at its output a code of the second address, which is sent to the address input of memory block 6. In this case, the output 7 of the block 6 PA

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The code of the second operation is generated, and the code of the second time interval is fed to the frequency control inputs of the generator 3.

If the input signal selected by multiplexer 8, the controlled signal from memory block 6 is present at the inputs 2 of the input unit 1, the operation of the device continues in accordance with the program recorded in the memory unit 6. Operation codes and time codes are formed; intervals between them. .

In the absence of a signal at the inputs 2, operation of the device is terminated before the arrival of this signal. Such a stop is possible in any device operation cycle, both within the cycle and at its end.

In the case of short-term interference at the input 2, the counter 4 does not have time to fill in with and zeroes after the end of the action; interference, therefore, the signal to the counting input of the counter 5 does not pass and the device does not fail.

When performing a pulse generator 3 according to the scheme in FIG. 3 on the third outputs of the memory block 6 in the calzd mode of operation of the device, the signal O is generated in only one of the bits, as a result one of the variable times of the setting resistors 16.1-16, n, the resistance of which determines the dwell time in this cycle, is connected with common wire.

When the input unit 1 is executed in the form of a multiplexer 8, its address inputs A1.,. The signal is fed from the second outputs of memory unit 6 or from the outputs of counter 5. As a result, an arbitrary or sequential connection of the input sensors to the reset input of counter 4 is provided. Suppose, in the first cycle of operation of the device, a multiplexer 8 is connected to the reset input of the counter 4. At the output of the memory block 6, the code of the first operation is generated. If this time step does not require the formation of a time lag, the memory unit connects to the generator a time resistor that provides the maximum oscillation frequency. When a sensor connected to the input D1 of the multiplexer B triggers, the counter 4 starts to fill with the maximum frequency for, for example, 5 .., 20 MO, which is quite enough for

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Claims (2)

Claim 1. A device for program control, comprising a memory unit, the first outputs of which are the outputs of the device, an input unit, the first inputs of which are connected to the inputs of the device, the second inputs to the second outputs of the memory unit, and the output is connected to the reset input of the first counter, the counting input of which connected to the output of the pulse generator, characterized in that, in order to increase reliability, a second counter is introduced into the device for program control, the counting input of which is connected to the output of the first counter, and the outputs are connected to address inputs of the memory block, the third outputs of which are connected to the frequency control inputs of the pulse generator. 2. The device according to p. ^ Characterized in that, in order to reduce equipment, the second inputs of the input unit are connected to the outputs of the second counter 'and the address inputs of the memory unit. physical 2 I Ί fig.Z