SU1401645A1 - Shaper of inclined-line video signal - Google Patents

Abstract

The invention relates to engineering. television The purpose of the invention is to simplify the device by eliminating the coding and programming blocks, the DAC and the analog coding block. The device contains lower-case delay blocks.

Description

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1 and personnel 2 sync pulses, a divider 3 frequencies, r-4 pulses, RS-triggers 5 and b, counters (C) 7 and 11, logical. block 10. Introduced el-t And 8 and el-t 9 delay. At the inputs of blocks 1 and

2line and frame pulses are given, which are formed by dividing the frequency of Mr. 4 pulses. Blocks

 and 2, respectively, delay the input sync pulses by an amount corresponding to the desired insertion point of the forming wedge. The impulse from block 1 sets the output of the short-circuit flip-flop 5 to one state. The impulse from block 2 sets the output of the RS-flip-flop 6 to one state, These signals ..

hitting the 2nd and 3rd inputs And 8, allow the passage of pulses 4 to the counting input of the CS operating in the countdown mode. With the passage of a number of pulses N equal to the code recorded in the C 11 bit inputs, the next pulse causes a C 11 pulse at the output of the transfer, which passes to the devices, the input of the divider 3, and also through the block IO to the input allowing reception of code C 1. As a result, the information from the bit outputs C 7 is rewritten to C 11 o This process is repeated K times, where K is the ratio, division is divided

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The invention relates to television technology and can be used to create special effects and test images in steam engines and test signal generators.

The purpose & invention is to simplify the device by eliminating digital

encoding and programming blocks, digital-to-analog converter and analog-coding block,

: The drawing shows a structural electrical driver circuit

: video signal slanted lines.

: The tilt-iHbix video line driver contains blocks 1 and 2 delay: CI horizontal and frame sync pulses, 3 frequency divider, 4 pulse generator, first 5 and second 6 RS triggers, first counter 7, element 1 and 8, delay element 9, logical block 10 and the second counter 11,

The device works as follows.

The inputs of the blocks 1 and 2 of the delay are supplied respectively to the horizontal and vertical pulses, which are formed, in general, by dividing the frequency of the pulses of the generator of the 4 pulses. Blocks 1 and 2 delays respectively. delaying the input sync pulse by an amount corresponding to the desired location for the introduction of the forming wedge.

Shpuls from the output of the block 1, the eyes of the lowercase b-impulses 5 hit the S-input of the first K8-trkg: herz 5, mustache, - tantalizes its output to the unit; condition., Analog of ICs kshulo. c yes block 2 delay frame) X sync pulses sets the output of the second B-3 thrunger 1, 6 to the e-cynical state- These signals, S, N, and the second and third inputs of the And 8 element, allow the passage of pulses from the generator 4 pulses to the counting the input of the second counter 11 operating in the countdown mode.

With the passage of the number of pulses N5 equal to the code recorded in the bit inputs of the second counter 1I, the next pulse causes the output pulse of the second counter AND pulses which passes to the output of the device, to the input of the frequency divider 8, as well as through the logic unit 10 - to the input of the permission to receive the code of the second counter 11, as a result of which the information from the bit outputs of the first counter 7 is copied to. bit inputs of the second counter 1 1. Such a process is repeated K times, where K is the divider division factor of 3 frequencies. In this case, K equidistant points in time are formed in this line, the distance between which is equal to N t, where сГ is the pulse following period at the output of the generator of 4 pulses.

After that, a pulse is formed at the output of the frequency divider, which is fed to the counting input of the first counter 7, reducing the content at its bit outputs by one. The same pulse, having entered the S input of the first RS flip-flop 5, sets the zero state at its output , what

Claims (1)

prohibits the passage of the counting pulse counter 7, this allows the indies from the generator output 4 pulses to the counting input of the second counter 1. This same pulse from the output of the frequency divider 3 through the delay element 9 goes to the first input of the logic block. ka 10 and, having got on its output, transfers the code from the bit outputs of the first counter 7 to the bit inputs of the second counter 11. This code is now equal to (). Therefore, in the next line, when the horizontal sync pulse from the output of delay unit 1 sets the first RS flip-flop 5 to one, K transfers the output of the second counter 11, the distance between which is (N-l) t. This process continues until the zero code is set at the bit outputs of the first counter 7. In this line, the distance between the pulses at the transfer output of the second counter 11 is T, After the appearance of K of such pulses, the pulse from the output of the splitter 3 frequency sets the output of the first RS-TpHr- s to the zero state of the output element And is connected to the outputs respectively the first and second RS flip-flops, whose S inputs are the inputs of the horizontal and frame sync signals, respectively, the output of the second 40 counter is the output of the video signal and connected via a frequency divider to the R input of the first RS flip-flop, the output of the frequency divider through the delay element is connected to the second 45 input of the logic unit, the output of which is connected to the synchronization input, the second counter, and the output of the first i counter is connected to the R input of the second lRS-flip-flop. Hera 5 appears at the counting input of the first counter 7, which results in a pulse transfer at its output, which sets the output of the second RS flip-flop 6 to the zero state and thus prohibits the passage of the counting pulses to the next frame. Since in the first counter 7 the transfer occurs, at its bit outputs a code N is formed again, which is copied to the second counter 11 by a delayed pulse from the output of the divider 3 frequencies. Thus, the device returns to its original state. The pulses from the transfer output of the second counter 11 form in N lines K lines, the distance between which in each subsequent line decreases. Since the information about the distance between the lines is contained on the bit outputs, the place on the CRT screen can be used to place any predetermined distances between the lines, which expands the scope of application of the device. A shaper-line video driver that contains a serially connected frequency divider and a first counter, a second counter and a logic block connected in series, a pulse generator, the first and second RS-flip-flops, characterized in that, in order to simplify the device by eliminating digital coding and programming blocks, a digital-analog converter and an analog-coding block, a delay element and an -I element are introduced, the output of the pulse generator through the AND element connected to the counting input of the second counter, the setup inputs of which are connected to the corresponding bit outputs of the first counter, second and third