SU1385318A1 - Frequency-manipulated signal receiver - Google Patents

Abstract

The invention relates to radio engineering and can be used to transmit data by the method of frequency manipulation of radio channels. The aim of the invention is to increase the noise immunity from "smooth interference". The device contains a limiting amplifier 1, r-2 filling pulses, synchronization block 3, counters 4 and 8, adder 5 modulo two, element 7, memory block 9, decisive block 10. To improve the noise immunity from "Smooth interference" a permanent storage device (ROM) 6 is inserted into the device, in which cells information, representing the logical state "zero and" one, is written with an address. The baths of the contents of the addresses of ROM 6 are produced sequentially by signals from the output of r-2 with a constant frequency. The addresses of the ROM 6 are controlled by signals from the outputs of the n-bit counter 4. 2 Il.

Description

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The invention relates to radio engineering and can be used for data transmission by the method of frequency manipulation and radio channels, mainly when processing low frequency subcarriers.

The symbol is minimized. The contents of the addresses of the ROM 6 are read out sequentially by signals (Fig. 2e) from the output of the generator 2 of pulses with a constant frequency. Address Management

The purpose of the invention is to increase the space of the ROM by signals from the resistance to noise from "smooth interferences. To a n-bit counter 4."

FIG. 1 shows a structural electron through an element AND 7 pulses (Fig. 2g), a partial scheme of the device proposed; on. FIG. 2 - timing diagrams, step on the input of the counter 8, clocked by signals from the output of the synchronization unit 3.

devices. 10 The number of pulses is counted per

The device contains an amplifier-ogreii- time from half a clock interval to

half the subsequent clock interval. The state of counter 8 is memorized in

block 9 and read the decisive block

discrete character. Solver unit 10 is also clocked by signals from the output of sync unit 3.

Claims (1)

Invention Formula A device for receiving frequency-manipulated signals comprising a series-connected amplifier-limiter I, a generator 2 pulses-filling, a synchronization unit 3, a second counter 4, an adder 5 modulo two, a constant memory device (ROM) b, element .g 10 at the next clock moment (Fig. 2h). And 7, the first counter 8, the memory block 9, is thus decided to know the block 10. The device works as follows. The input mixture of noise and the frequency-controlled signal with a control index of 0.5, whose frequencies are equal to 2Ji / T and ff / T, respectively, is fed to the input of the limiting amplifier L, where it is converted into a sequence of square pulses Fig. 26), which the reader, the synchronization unit, the adder make at the input of the adder 5 modulo two, the I element, the first counter, two, the second input of which is supplied by the memory block and the decision block, and Geted rectangular pulses (Fig. 2c) with a pulse filling pulse and second 3 block synchronization. Output directors of the counter, characterized in that, for the purpose of the carbon impulses (Fig. 2d) of the adder 5, the gains and the noise immunity from the "smooth" input to the input element of the And 7 element, and that is the interference, are permanently memorized in relation to the counting device, the first output to the pulses (Fig. 2e) arriving at the other filling pulse generator is connected to the first input of the element And 7c of the ROM output b. with the first input of the second counter, the second In the cells of the ROM 6, the input is connected to the first input of the formation, which is a logical synchronization unit, the second output of which is the state “O and” 1. This information 35 is connected to the second inputs of the first one, located in the cells of ROM b, so that the counter and the decisive block, the output frequency of the occurrence of state "1 at times close to the end and beginning of the clock interval, is lower than at times close the counter is connected to the address inputs of a persistent storage device whose read input is connected to the middle of the clock interval. This brought 40 with the second. pulse generator output It leads to the fact that signal sections close to the moments of signal wave crossing through the zero level (Fig. 2a) are processed with a lower weight and, consequently, their effect on the overall noise immunity of filling, the permanent memory device is connected to the second input element And, the third output of the synchronization unit is connected to the second input of the modulo two. The symbol is minimized. The contents of the addresses of the ROM 6 are read out sequentially by signals (Fig. 2e) from the output of the generator 2 of pulses with a constant frequency. Address Management  The ROM B is effected by signals from the outputs of the n-bit counter 4. Past  through the element And 7 pulses (Fig. 2g) step on the input of the counter 8, clocked by signals from the output of the synchronization unit 3.  The number of pulses is counted for block 9 and read the decisive block 10 at the next clock point (Fig. 2h). Thus, it is decided to sign discrete character. Solver unit 10 is also clocked by signals from the output of sync unit 3. Invention Formula A device for receiving frequency-manipulated signals, containing a series-connected amplifier-limon10 at the next clock point (Fig. 2h). Thus, it is decided to sign A reader, a synchronization unit, an adder modulo two, an element I, a first counter, a memory unit and a deciding unit, as well as a generator of filling pulses and a second counter, characterized in that, in order to improve noise immunity from "smooth interference" , a permanent memory device is inserted, the first output of the filling pulse generator is connected to the first input of the second counter, the second input of which is connected to the first input of the synchronization unit, the second output of which is connected to the second inputs of the first counter and decision unit, out odes of b- A reader, a synchronization unit, an adder modulo two, an element I, a first counter, a memory unit and a deciding unit, as well as a generator of filling pulses and a second counter, characterized in that, in order to improve noise immunity from "smooth interference" , a permanent memory device is inserted, the first output of the filling pulse generator is connected to the first input of the second counter, the second input of which is connected to the first input of the synchronization unit, the second output of which is connected to the second inputs of the first counter and decision unit, out odes of b- the counter is connected to the address inputs of a persistent storage device whose read input is connected  with the second. pulse generator output filling, the output of the permanent storage device of the 1st device is connected to the second input of the element And, the third output of the synchronization unit is connected to the second input of the modulo two. but F 3