SU1374175A1 - Device of digital former of signals with double relative phase modulation - Google Patents

Abstract

The invention relates to the field of communication and improves the accuracy of the formation of the output signal envelope (SIR). The device contains a serial-parallel converter 1, memory blocks 2 and 7, a shift register (PC) 3, a multiplexer 6, a DAC 8. PCs 4 and 5 reintroduced, control G-9 and counter 10. Increased accuracy in shaping the SMF this is achieved due to the fact that in block 7 all possible variants of the amounts are stored, 2 Il.

Description

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ten

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The invention relates to communications and may find application in data transmission systems and remote control.

The aim of the invention is to improve the accuracy of the formation of the envelope of the output signal.

Fig. 1 shows the structural-electrical circuit of the device; Fig. 2 shows the voltage patterns that show his work.

The device contains a series-parallel converter I, a first memory block 2, a first 3, a second A and a third 5 shift registers, a multiplexer 6, a second memory block 7, a digital-to-analog converter 8, a control generator 9 and a counter 10.

The device works as follows.

The input sequence in the series-parallel converter 1, controlled by signals from the second output of the control generator 25 (Fig. 2a), is divided into dibits, which are fed to the first memory block 2. It converts the incoming information into a relative code. The previous production code is stored in a two-bit first register 3. At the output of the first memory block 2, there are in-phase and quadrature components that determine the coordinates of the transmitted signal. These components are recorded respectively in the shift registers 4 and 5, where they are stored for four clock intervals. In each registers 4 and 5 of the shift, the advancement of information is carried out with the arrival of

1374175 2

on the clock input of the trailing edge of the pulse sequence (Fig. 2d) from the first output of the control generator 9. Signals from the outputs of the bits of shift registers 4 and 5 in the parallel code are sent to the information inputs of the multiplexer 6. The signal at the output of the driver can be represented in the form

M-t

S (KTg) a (KT5-iT5) g (iT) X

X soz. (OCTT5) + §: b (KT -iTg) X

i 1

X g (iT) sin (toKT)

(one)

.Where

g (iT,)

-e / .DA.1.o. t. e j

- counts of the impulse response;

a (CTD-iT),

b (KTg-iTg) - in-phase and quadrature counts of the input sequence, respectively; sampling period;

IT1,

cosO |, kT

five

orthogonal carrier oscillations.

thirty

35

In the device, the sampling frequency fg 1 / Tg is equal to 7200 Hz, and the carrier frequency is equal to 1800 Hz, i.e. There are 4 discrete readings of this oscillation per period of carrier oscillation. Consequently, during the time between two counts, the phase (, THIS oscillation changes by

2 R / 4 T / 2, and taking into the first reading and sof at f 0, we obtain, respectively, O and 1 and further for other phases that are multiples of fr / 2 (1; 0), (0; -1), (-1; 0), 40 hide it, rewrite the expression (1) in the following form:

S (KT5) fla (KT, -iTs) g (iT5) 2gn cosKKT5) + + b (KTs-iTg) g (iTg) (),

where () (uHKTs)

This shows that in the output signal there is only one of the sums of Prash (2) - either cosine or sine, and the carrier wave takes only two absolute values of zero or one, and in this case the sign of the carrier frequency, which determines the sign of the received amounts.

five

0

five

X soz. (OCTT5) + §: b (KT -iTg) X

i 1

X g (iT) sin (toKT)

(one)

.Where

g (iT,)

-e / .DA.1.o. t. e j

- counts of the impulse response;

a (CTD-iT),

b (KTg-iTg) - in-phase and quadrature counts of the input sequence, respectively; sampling period;

IT1,

cosO |, kT

five

orthogonal carrier oscillations.

In the device, the sampling frequency fg 1 / Tg is equal to 7200 Hz, and the carrier frequency is equal to 1800 Hz, i.e. There are 4 discrete readings of this oscillation per period of carrier oscillation. Consequently, during the time between two counts, the phase (, THIS oscillation changes by

2 R / 4 T / 2, and taking into the first reading and sof at f 0, we obtain, respectively, O and 1 and further for other phases that are multiples of fr / 2 (1; 0), (0; -1), (-1; 0), behind this, rewrite expression (1) in the following form:

(2)

or -1 if OTsKT5 TSK + P. if o, (2K + 1) or -1, if (OnKT5 T / 2 (2K + 1)

if (0ts KTs V (K + 1).

Thus, the exclusion of one of the sums in the output signal leads to a decrease in the formation error 55 and does not increase the formation accuracy.

The duration of the impulse response of four, the clock interval gives the Nyquist-satisfying output spectrum of the signal. Consequently, the last four values of the input sequence of one of the shift registers 4 or 5, which correspond to one of the sums, for example, the blue-phase component, participate in the formation of the output sample.

S (t) a, g (t-T) + a (t-2T) + a, g (t-3T) +

+) cosu, t, (3)

Where

but. - input sequence

common mode; g (t-nT) -pulse characteristic

T is the period of manipulation. Here, 0 can be +1 or -1, similarly for the quadrature component. The impulse response is also obviously determined and, therefore, the sum of the form (2) or (3) is known in advance, i.e. The output signal on the device's output has a fixed set of values that are stored in the second memory block 7 and output to the digital-to-analog converter 8 at appropriate points in time. To determine the desired value, the output of one of the 4 or 5 shift registers is connected via multiplexer 6 to the first inputs of the second memory block 7, to the second input of which a square wave with a frequency of 1800 Hz is applied, which determines the sign of the carrier frequency, and the third input contains the count number on the beat. With the selected sampling frequency fg of 7200 Hz and the manipulation speed equal to fg, 1200 Water, for one manipulation period (cycle) there are 6 times of the impulse response. Thus, at the specified address, the output sample is selected for the digital-analogue converter 8. All the variants of the form (2) are calculated .. are removed with high accuracy and recorded in the second memory block 7, which allows to exclude the accumulation of the convolution result (2 ) in the device, since every summation occurs

a resolution that increases with increasing number of summations.

At the sixth output of the controlled oscillator there is a frequency of 7,200 Hz (Fig. 2a), corresponding to the sampling frequency. Switching multiplexer 6 is made with a frequency of 3600 Hz from the third control output,

0

five

0 5 g Q

five

0

Generator 3 (Fig. 26), since the in-phase and quadrature components are selected alternately. The carrier sign is determined by the frequency 1800 Hz from the fourth output of the control generator 9 (FIG. 2b). First, the cos and sin values take turns, equal to +1, then -1, and so on.

The new input values are written into the registers 4 and 5 of the shift under the negative edge of the 1200 Hz frequency of the first output of the control generator 9 (.2a), which determines the new cycle of formation of six output samples with a sampling frequency of 7200 Hz from the sixth output of the control generator 9 (figa). After the sixth trailing edge, counter 10 is zeroed and the counting starts over. The device is transferred to operation by closing the toggle switch in the control generator 9, until then all of its counters are in the zero state and do not respond to the incoming frequency.

Such a combination of blocks allows one to obtain a device for the digital formation of signals with a double relative phase modulation with an increased accuracy in the formation of the envelope of the output signal. This makes it possible to use a digital signal shaping device with double relative phase modulation when building small-sized data transmission equipment over degraded channels with a speed of 2400 bit / s, I

This device eliminates the accumulation of elementary signal samples and, therefore, the corresponding errors are absent, and the operand width is also increased to 12 double bits and only polarity is used as carrier oscillation, which together allows data to be transmitted on degraded channels. . An increase in the accuracy of the formation of the output envelope is achieved due to the fact that the memory block contains all possible options for the amounts that can be formed depending on the input sequence, calculated with high accuracy and rounded to the required size, as well as the absence of one component shaping envelope you513

the drive signal and multiplication by the sign of the carrier oscillation in view of the choice of the multiplicity of the sampling frequency of the impulse response to the frequency of the carrier oscillation.

Claims (1)

DETAILED DESCRIPTION OF THE INVENTION Digital Signal Mode Amplifier with double relative phase modulation, comprising a digital-analog converter, a first shift register and a serial-parallel converter, the output of which, as well as the output of the first shift register, are connected to the first and second inputs of the first memory block. and a serially connected multiplexer and a second storage unit, the first one in which the series-parallel converter is an input to the device, characterized in that she- forming precision audio output envelope signal, it introduced a control generator, a counter and the second and third shift registers, whose outputs are connected to data inputs of the multiplexer, a first output / g 3 5 b t gyggi V6 vz Fig 2 Compiled by O. Andrushko Editor NLIvidka Tehred I.Popovich Order 600/43 Circulation 660 Subscription VNIIGTI USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushsk nab. 4/5 756 The first memory block is connected to the information input of the second shift register and to the first information input of the first shift register, the second OUTPUT of the first memory block is connected to the information input of the third shift register and to the second information input of the first shift register, the information input and output of the counter are connected respectively with the control input of the digital-to-analog converter and with the second input of the second memory block, the output of which is connected to the information input of the digital-analog converter, t Actual inputs of the first, second, and third shift registers are connected to the first output of the control generator, the second, third, fourth, five, and sixth outputs of which are connected respectively to the second input of the series-parallel converter, to the third input of the multiplexer. the second memory block, with the installation input of the counter and with the control input of the digital-analog converter, the output of which is the output of the device. / 2 J 5 ё b rTJTJlJ T rLrLrL. L L. Proofreader O ravtsova