SU1368807A1 - Digital phase meter - Google Patents

Abstract

The invention can be used to create high-precision phase-to-code converters for control digital computing systems. The purpose of the invention is to improve the measurement accuracy at a high rate of change in the phase shift of the input signals. The phase meter contains the formers 1,2,

Description

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8-11 pulses, inverter 12, shift register 13, frequency multiplier 14, keys 15-18 and 31, triggers 19-21, controlled inverters 22 and 23, oscillator 24 clock pulses, synchronization unit 27, OR element 28, counters 29 and 32, p-bit registers 30, (p-1) -disk inverters 33 and 2n-bit multiplexer 36. By introducing a second (p-1) -disk inverter 33, 2n-bit multiplexer 34 The 2p-bit adder 35 and 2p-bit registers 37 and 38 is made possible by calculating the function Cpop; produce an algebraic sum operator over the intermediate measurements of the phase shift of the input signals. This is equivalent to an increase in the measurement time while preserving the uniqueness and continuity of the phase characteristic, and, therefore, without gross errors as a result of the measurement. 3 il.

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The invention relates to a measurement technique and can be used to create high-precision digital phase meters, as well as high-precision phase to code transducers for control digital computing systems.

The purpose of the invention is to improve the accuracy of measurements at a high rate of change in the phase shift of the input signals.

FIG. 1 shows a block diagram of a phase meter; in fig. 2 - phase characteristics of the known (solid line) and the proposed (dash-dotted line) phase meters; in fig. 3 is a block diagram of a synchronization unit.

The digital phase meter contains the first and second shaper 1 and 2 pulses, the first shaper 1 of the pulses consisting of the first amplifier limited in series 3, the first comparator 4 and the shaper 5, the second pulse shaper 2 contains the second amplifier 6 terminally connected in series and the second comparator 7 , third 8, fourth 9, fifth 5 and sixth 11 pulse shapers, inverter 12, shift register 13, frequency multiplier 14, first 15, second 16, third 17 and fourth 18 keys, second, first and third rigger 19-21, first and second controllable inverters 22 and 23, the oscillator 24 clock pulse shaper consisting gdy of pulse sequences 25 and generator 26, the block 27

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synchronization, element SHS 28, first counter 29, n-bit register 30, fifth key 31, additional counter 32, (n-1) -disp dnv1 inverter 33, first multiplexer 34, adder 35, second multiplexer 36, first and the second 2p-bit registers 37 and 38, and the output of the comparator 4 is connected to the first input of the controlled inverter 22, the second input of which is connected to the output of the counter 32 and to the second input of the controlled inverter 23, the output of the former 5 is connected to the first inputs of the keys 16 and 17, the second inputs of which are connected to the second input of the key 31, the reset input the counter 29 and the third output of the synchronization unit 27, the third input of the key 16 is connected to the output of the inverter 12, the input of which is connected to the third input of the key 17 and the output of the shift register 13, the output of the comparator 7 is connected to the input of the frequency multiplier 14, the inputs of the formers 10 and 11 and the first the input of the shift register 13, the second input of which is connected to the output of the frequency multiplier 14, the output of the key 1b is connected to the first input of the trigger 19, the second input of which is connected to the output of the key 17, and the output of the trigger 19 to the first input of the key 31, the output of the last socket Inonii to the first input of the counter 32, the second input of which is coupled to the output of a tenth sync block 27, the output of inverter 22 is connected to the input of the pulse 8 and 9.

the outputs of which are connected to the first inputs of the trigger 20 and 21, respectively, the second input of the trigger 20 is connected to the output of the pulse driver 11 and the third input of the key 31, the output of the trigger 20 is connected to the first input of the key 15, the second input of which is connected to the second output of the synchronization unit 27 and the first the input of the key 18, the third input of the key 15 and the second input of the key 18 are connected respectively to the first and second outputs of the imaging unit 25 pulse sequences, and the third input of the key 18 is connected to the output of the trigger 21, the output of the generator 26 is connected to the second input The synchronization block 27 and the pulse generator sequence input 25, the first input of the block 27 is connected to the output of the pulse driver 10, the outputs of the keys 15 and 18 are connected to the first and second inputs of the OR element 28, respectively, the output of the OR element 28 is connected to the counter 29, the outputs of which The (t + 1) th to (t-1) -th are respectively connected with the inputs of the first through (p-1) th register 30, and the t-th output - with the first input of the controlled inverter 23, the output which is connected to the n-th input of the register 30, the outputs of the register 30 from the first to (n-1) -th connected to the inputs of the inverted Ora 33, the register entry input 30 is connected to the first output of synchronization unit 27, the outputs of inverter 33 are connected to the first (n-1) younger bits of multiplexer 34, the second inputs of which are connected to the outputs of register 38, and the first inputs of bits from n 2d through 2 are connected to the output of the nth register bit 30, the control inputs of the multiplexer 34 are connected to the fourth and fifth outputs of the synchronization unit 27, the first inputs of the adder 35 are connected to the outputs of the multiplexer 34, the second outputs are k outputs of the register 37, the input records which is attached to the virgin output of block 27 syn synchronization, the first inputs of the multiplexer 36 are connected to the output from (n + 1) -th to 2-th bits of the adder 35, and the second inputs to the source of the zero logic level, the inputs of the register 38 are connected to the outputs of the adder 35, the input of the register entry 38 connected to the sixth output of the synchronization unit 27, the inputs of the lower n bits of the register 37 are connected to the outputs

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register moves 30, and the high-order inputs to the outputs of multiplexer 36, the control inputs of which are connected to the seventh and eighth outputs of block 27.

Block 27 contains a key 39, a counter 40, a pulse former 41, an OR element 42, a trigger 43, a second key 44, a second counter 45, an inverter 46, a second trigger 47, a second inverter 48, a third trigger 49, a third key 50, a second driver 51 pulses, frequency divider 52, third counter 53, decoder 54, fourth trigger 55, second and third elements OR 56 and 57, and fifth trigger 58, the first input of counter 40 connected to the output of key 39, the first input of which is the second input of the block 27 synchronization and is connected to the input of the divider 52 frequency, the second input of the counter 40 coupled to the first output of the flip-flop 47 and a third

5 in the code of the synchronization unit 27, the first input of the counter 45 is connected to the first input of the trigger 47 and to the output of the key 44, the first input of which is connected to the first input of the block 27, and the second input to the first output of the trigger 43, the first input of the element OR 42 is connected to input Work / Stop block 27 synchronization, as well as to the input of the inverter 48 and the first input of the trigger 49, the second input element OR 42 is connected to the first output of the block 27 synchronization and the output of the driver 41, the input of which is connected to the output of the counter 40, the output of the element OR 42 is connected to the second exits Meters withstand 45, flip-flops 47 and 43 and output to a tenth sync block 27, the first input-flop 43 is connected to the first output of the flip-flop 47, inverter 46

g is connected between the output of the counter 45 and the third input of the trigger 47, the second output of the trigger 43 is connected to the second output of the block 27 and the second input of the key 39, the output of the inverter 48 is connected to the first input of the key 50, the second input of the trigger 49 is connected to the first input of the trigger 58 and the start of the cycle of the block 27, the output of the trigger 49 is connected to the second input of the key 50, the output of which is connected to the first input of the counter 53 and the first input of the trigger 55 through the pulse shaper 51, the output of the frequency divider 52 is connected to the second input of the counter 53, the outputs of the co5

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the first and second outputs of the latter are connected to the ninth and sixth outputs of block 27, the third output is connected to the second input of the trigger 55, the third input of which is connected to the fourth output of the decoder 54, the second input of the trigger 58 and the third input of the counter 53, The first and second outputs of trigger 55 are connected to the first inputs of the OR 56 and 57 elements, respectively, the first output of the trigger 58 is connected to the second inputs of the OR 56 and 5 elements and the seventh output of block 27, the second output to the eighth output of block 27, the outputs of the OR elements 56 and 57 with are united with the fourth and fifth outputs of block 27.

The digital phase meter operates as follows.

Sinusoidal or rectangular voltages X, and X are applied to the first and second formers of 1 and 2 pulses, with the voltage X being the reference.

The input signals, having passed through the first and second limiting amplifiers 3 and 6, are amplified and symmetrically limited in amplitude. Using the first and second comparators 4 and 7, the input signals are converted into square voltage with levels compatible with the series of chips used.

The full range of values of the measured phase shift C is divided into two areas: 0 ± 90 ° and 180190 °.

The initial value of the phase shift, which determines which region i falls into (, is found by averaging over several periods of input signals in the preparation interval when the synchronization unit 27 removes the key lock 16 and 17, simultaneously resetting the counter 29. Keys 15 and 18 at this moment blocked.

The shaper 5 produces a short pulse at the moment when the leading edge of the X signal appears. This pulse hits the first inputs of keys 16 and 17, the third inputs of which are outputted from the output of the shift register 13 are given a signal X. shifted by 1/4 of the period, and the key 16 - via inverter 12. Pulse with pulse frequency f, generated by multiplier, are sent to clock input of shift register 13

14 from signal X, and, if 5, 16, then the output of the shift register 13 is the output of its fourth bit. In this case, oscillations of the boundaries of the regions occur within 1/16 of the periods of the input signals, regardless of the frequency fg, and practically do not affect the measurement accuracy. If q is in the first region, the pulse passing through the key 16 hits the first input of the trigger 19. When tf is in the second region, the pulse hits the second input of the trigger 19, which remembers the initial value of the phase shift determined during one period of the input signals. At the first input of the counter 32, in which the initial value of the phase shift, previously set to the zero state by the signal from the tenth output of the synchronization unit 27, is averaged, the key 31 receives pulses from the generator 11 during the preparation interval defined by the unit 27, provided the presence of a logical unit at the output of the trigger 19. The number of periods of the input signals included in the preparation interval is 2, where k is the number of bits of the counter 32. If the initial value of the phase shift corresponding to the logical unit At the output of the trigger 19, more than half of the periods of the input signals entering the preparation interval, a logical unit appears at the output of the counter 32, which indicates that cf is in the second region (near the point of discontinuity of the phase characteristic).

At the end of the preparation interval, the measurement takes place. In this case, if Cpj (is in the first region, signal X, passes through controlled inverter 22 without inversion and hits the inputs of drivers 8 and 9. Signal X hits the inputs of drivers 10 and 11. The drivers 8 and 10 produce pulses bound to the leading edges of the signals X and X, and the drivers 9 and 11 to the leading edges of the Triggers 20 and 21 form phase intervals and control the keys 15 and 18, which are unlocked at this moment. On the second inputs of the keys 15 and 18 from the generator outputs 24 clock pulses are received by a sequence of countable impu sov, shifted

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180 ° phase relative to each other. Passing through the keys 15 and 18, these sequences fall on the element OR 28 and further on the clock input of the counter 29.

By the measurement interval, the synchronization unit 27 blocks the keys 15 and 18 and by storing the write strobe of the contents of the counter 29 into the output register 30. If Cf is in the first area, then the most significant bit of the output code N is transmitted through inverter 23 without inversion.

With the beginning of the nearest reference signal period, the next measurement cycle occurs, while if cf is in the second region, signal X is inverted by the control of inverter 22, which is equivalent to introducing an additional phase shift of 180 ° C to compensate for the introduced phase shift. The d code N ,, is inverted by inverter 23.

The part of the digital phase meter, in which information is accumulated, consisting of inverter 33, adder 35, multiplexers 34 and 36, and registers 37 and 38, starts from the second period of the Work / Stop signal, counting Start the cycle.

In the second period of the Run / Stop signal, the code from the output of register 30 is fed to the inputs of the lower bits of register 37. The inputs of the higher bits of register 37 receive the logical zero level, since in the second period of the Run / Stop signal, the second inputs of the multiplexer are connected 36. Block 27 transmits the write signal to register 37. The number recorded in register 37 goes to the second inputs of the adder 35, the first inputs of which receive the logical zero level, since the multiplexer FOR is blocked by signals output by the block 27. Thus azom, output from the adder 35 to the inputs of the register 38 is supplied with the number of output register 30, folded to zero. Block 27 vfabatas the signal recording in the register 38.

In the third and subsequent leriods of the Run / Stop signal, multiplexer 36 switches to a position where information can be passed from the output of the adder 35 to the inputs of the register 37. To the second inputs

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(n-1) low-order bits of multiplexer 34 receives an inverted signal from the outputs (n-1) of lower-order bits of register 30, and the inputs (n + 1) of high-order bits receive the value of the n-th bit from the output of register 30. This the code goes to the first inputs of the adder 35, since block 27 connects the first inputs of the multiplexer 34. The code corresponding to the value of the phase shift measured in the previous measurement period is fed to the second inputs of the adder from the output of register 37. At the output of the adder 35, a code is generated corresponding to the value

, m; + + then; -,,, (1) the most significant bits of which are received at the inputs of the most significant bits of the register 37.

The synchronization unit 27 provides for the formation of a recording strobe in register 37. Thus, in register 37, the number corresponding to

(-I i.MG- -CH "p; - FFOO + tp ,,;. (2)

Next, the multiplexer 34 switches to the opposite position, and the code corresponding to the accumulated measurement in the previous cycles from the output of the register 38 goes to the first inputs of the adder 35. The code from the output of the register 37 enters the second inputs of the adder 35. At the output of the adder, a code is generated that is written to register 38 due to the recording strobe produced by block 27.

Thus, in register 38, the number appears in accordance with formula (2).

The synchronization unit 27 operates in the following manner.

Before work begins, a start of cycle signal is given. In this case, the Work / Stop input must be a logical one. Such a combination is

The bank ensures that all triggers, except trigger 55, and counters, except counter 53, are set to the zero state. When a zero level appears at the Work / Stop input, the trigger 47 is energized by the first impulse from the output of the driver 10 and the preparation interval begins.

The pulses from the output of shaper 10 passing through key 44 are counted by counter 45, the number of bits

which is equal to K. When the counter 45 accumulates 2 pulses, a logical zero appears at its output, which through inverter 46 resets trigger 47, trigger 43 is activated, the preparation interval ends and the measurement interval begins. The duration of the measurement interval is determined by the time of the setting counter 40, to the clock input of which, via the key 39, impulses are received from the output of the generator 26 of pulses. The shaper 41, at the end of the measurement interval, produces a short pulse that serves as a write gate to the register 30 and passes through the OR 42 element, resetting the trigger 43.

In this case, the first measurement interval ends. On the leading edge of the 20-fold summation over the Run / Stop signal interval (i.e., when the Run / Stop signal returns, the trigger 49 is fired, thereby allowing the Run / Stop signal to pass through the switch 50 to the pulse shaper 51, which produces short pulses for resetting flip-flop 55 and counter 53. At the same time, the output of decoder 54 stops blocking counter 53, to the clock input of which through the frequency divider 52 pulses are received from the output of generator 2b of pulses. Since the trigger 58 is reset, the logical unit level at its first output blocks the OR 56 and 57 elements, the outputs of which block multiplexer 34. In addition, the signals from the outputs of the trigger 58 set the multiplexer 36 to the state at which its second inputs are connected. When the counter 53 P1 accumulates pulses, a signal is generated at the first output of the decoder 54, which provides a write strobe to the register 37, and when P2 accumulates pulses, the second output of the decoder creates a write strobe in the register 38 (). When the counter 53 accumulates pulses, the trigger 55 triggers with the signal from the third output of the decoder 54, and with the accumulation of P4 pulses () the trigger 55 is reset with the signal from the fourth output of the decoder 54, the trigger 58 recharges and blocks the second count of the counter 53. . The operation in the third and subsequent periods of the Work / Stop signal differs from the second period only in that the trigger 58 is cocked and does not block the OR 56 and 57 elements; moreover, the signals from the outputs of the trigger 58 are multiplexed to the state in which the first entrances.

Thus, an increase in the measurement accuracy at a high, as compared with the measurement time, rate of change of the phase shift of the input signals and in the case where during the measurement time

the value of the phase shift is beyond the scope of the unambiguity of the measuring device, achieved by the fact that by calculating the functions srsor; it is possible to perform an operation with algebetic measurements of the phase shift of the input signals, which is equivalent to an increase in the measurement time while preserving the uniqueness and continuity of the phase characteristic and, therefore, without gross errors in the measurement result.

Claims (1)

Invention Formula A digital phase meter containing a clock generator, a synchronization unit, the first and additional counters, a register, five keys, three flip-flops, a shift register, a frequency multiplier, an inverter, two controlled inverters, six pulse shapers, an OR element, the inputs of the first and second pulse shapers are connected respectively to the first and second input buses of the phase meter, the first output of the first pulse shaper is connected to the first input of the first controlled the second output to the first inputs of the second and third keys; the output of the second pulse driver is connected to the inputs of the fifth and sixth pulse drivers, to the first input of the shift register and through the frequency multiplier to the second input of the shift register, the output of which is connected to the second input of the third key and through the inverter with the second inlet of the second key, the output of which is connected to the first input of the second trigger, the second input of which is connected to the output of the third key, the output of the first controlled inverter through 1113 The third and quarter pulse generators are connected respectively to the first inputs of the first and third flip-flops, the outputs of which are connected to the first inputs of the first and fourth keys, the second input of the third trigger is connected to the output of the fifth pulse shaper and the first input of the second the third inputs of the first and fourth keys, whose codes are connected respectively to the first and second inputs of the OR element, the output of which is connected to the input of the first digit of the first counter, the second and third synchronization outputs, the second input of which is the inverter, the first (2π-bit) the second one is connected to the first output of the type generator, the second (p-rar dny) clock pulse nullator, the second vyplexor, 2n-bit adder, two clock of the synchronization unit are connected to the 2n-bit register, and the inputs The second inverter is connected to the outputs 15 of the first register, the outputs of the second inverter to the first inputs (p-1) of the lower bits of the first multiplexer; the first inputs of the first multiplexer from the nth to 2nth are connected to the clock generator the pth output of the first register, dinene, respectively, with the second inputs of the first multiplexer, the connectors of the first and fourth keys, are subtracted to the first inputs of the adder, and the inputs of the first counter from the (m + 1) th control - to the fourth and fifth to the (ha-1) th connected to the inputs of the register pvoy on (n-1) -th, respectively, and the ha-th output of the first counter is connected to the first input of the second controlled inverter, the output of which is connected to the n-th input of the register, the recording input of which is connected to the first output of the synchronization unit, connected to the synchronization unit inputs , the outputs 25 of the adder are connected to the inputs of the second register, and the outputs of the second register are connected to the second inputs of the first multiplexer, the first inputs of the second multiplexer are connected to the outputs of n 30 most significant bits of the adder, the second inputs of the second multiplexer are connected to zero To their logical level, the control inputs to the seventh and eighth outputs of the synchronization unit. at the outputs of the synchronization block, the outputs 25 of the adder are connected to the inputs of the second register, and the outputs of the second register are connected to the second inputs of the first multiplexer, the first inputs of the second multiplexer are connected to the outputs of the 30 most significant bits of the adder, the second inputs of the second multiplexer are connected to zero logic level, control inputs to the seventh and eighth outputs of the synchronization unit. The tenth output to the installation input of the additional counter, the output of the sixth driver is connected to the second input of the first trigger, the first output to the inputs of the higher ones, the fifth input of the fifth key is connected to the third register triggers, the inputs and junior inputs the second and third keys, the reset input of the first counter and the third output of the synchronization unit, the second input of the fifth key by the 40 inputs of the first adder, the replacement inputs to the second trigger output, and the second and third register inputs to the sixth output The rods are connected to the sixth and ninth outlets, the output of the fifth key is connected by the synchronization unit to the first input of the additional counting unit. The third bits of the third register are connected to the outputs of the first register, the outputs of the third register are connected to the second The output of the second counter is connected to the second inputs of the first and second controlled invs (rtori, which is due to the fact that, in order to improve the accuracy at a high rate of change, :). phase shift of the input signals, the second (n-1) -discharge bit is additionally introduced into it The second inverter is connected to the outputs of the first register, the outputs of the second inverter are connected to the first inputs (n-1) of the lower bits of the first multiplexer, the first inputs of the first multiplexer from the nth to 2n-th are connected to the nth output of the first register, the outputs the first multiplexer is connected to the first inputs of the adder, and the control inputs to the fourth and fifth the outputs of the synchronization block, the outputs of the adder are connected to the inputs of the second register, and the outputs of the second register are connected to the second inputs of the first multiplexer, the first inputs of the second multiplexer are connected to the outputs of the higher bits of the adder, the second inputs of the second multiplexer are connected to the zero logic level, the control inputs - to the seventh and eighth outputs of the synchronization unit. and the outputs to the inputs n of the higher bits of the third register, the inputs n and the junctions of the first adder, the write inputs of the second and third registers are connected to the sixth and ninth outputs of the synchronization unit, respectively. and the outputs to the inputs n of the higher bits of the third register, the inputs n and the junctions of the first adder, the write inputs of the second and third registers are connected to the sixth and ninth outputs of the synchronization unit, respectively. The third bits of the third register are connected to the outputs of the first register, the outputs of the third register are connected to the second