SU1365289A2 - D.c.voltage converter - Google Patents

Description

The lecturer – emitter of transistors is equal to zero, and consequently, power is not allocated to them at the moments of their switching. Voltage regulation on the load is carried out due to the time-displacement of the control signals by the transistors (and, consequently, the voltages on the transformers) of the main and additional inverter cells.

2 Il.

The invention relates to electrical engineering, can be used in systems of secondary power supply and automation, for converting and regulating DC voltage, and is an improvement of the invention according to the author. St. No. 1257778.

The purpose of the invention is to increase reliability by reducing the peak power dissipated in power transistors in transient conditions.

FIG. 1 is a schematic diagram of the proposed converter; in fig. 2 - voltage and current diagrams for the operation of the converter.

The constant voltage converter (Fig. 1) contains the first and second inverter cells 1 made on transistors 2 and 3. Transformers 4 and 5, diodes 6-9 and capacitor 10 and controlled from the main control unit 11, the outputs of which are connected to The control inputs of transistors 2 and 3. The third and fourth inverter cells 12 are made similarly to the first and second cells on transistors 13 and 14, transformers 15 and 16, 17-2U diodes and capacitor 2. The capacitors 22 and 23 are connected to the input terminals. The transistors are controlled by an additional control unit 24. The phase-shifting device 25 controlling the input is connected to the auxiliary output of the control unit 11, and the output to the control input of the control unit 24. Output windings 26-29 of transformers 4, 5, 15 and 16 are connected in pairs in series and through diodes 30 and 31 and filter 32 are connected to load 33.

The Converter operates as follows.

0

five

0

five

five

0

five

0

FIG. 2 shows transistor control pulses 2, 3, 13 and 14.

 j3 s The pulses Uuj and UM of transistors 2 and 3 of the first and second cells are mutually shifted by time and, while the pulses of Uu and Uu, 4 by transistors 13 and 14 of the third and fourth cells by time and tj-tfe, which during operation remain unchanged. The control pulses U (j (U (,) and, "(and,) are shifted by phase-shifting device 25 by time) depending on the operating mode of the converter. The voltages on transformers 4 and 15 (Uj and and y) and total voltage across the series-connected windings 26 and 28 of transformers 4 and 5 (UE).

Let the transistor 2 of the first cell turn on at the moment t О. Since the current through the transistor 2 is determined by the voltage AND (in the interval tj the energy is transmitted to the load), at the time t 0 the current i 0 through this transistor is zero and at the time of its switching on the power is not released in it. At the end of the pulse at the moment tt, the voltage on the capacitor 10 10 - (polarity +, -) j.flo which it charged (up to the voltage on the capacitor 22) from the transformer 5 at the moment of pause, before turning on the transistor 2, - The collector - emitter junction of the transistor 2 Ug is zero, and the transistor turns on at zero voltage. At the interval tj- t, the transformer 4 is turned off, the polarity of the voltage on the primary winding changes, and the stored capacitor 10 is recharged to the opposite polarity +, -, creating favorable conditions for switching on and out

switching off the transistor 3 of the second cell At the time t tj, the transistor 13 turns on, although the TC through it is not equal to zero, but the voltage of the collector-emitter circuit is equal to zero, since the capacitor 21 is charged with the energy of the transformer,

Matora I6 during the power of the moment of switching on the transistor 13 with polarity H, -. at tt, the voltage on the load U. drops to zero, and the current through the transistor 13 drops exponentially, tends to the current, magnetized at the end of the pulse, and since the voltage on the capacitor 2 is equal to the voltage on the capacitor 23, the voltage at the junction, the collector - emitter of transistor 13 is zero, and the power at transistor 13 is not increased when it is turned on.

/

When the load current decreases, the accumulated energy in the transformers decreases and, therefore, capacitors 10 and 21 may not be charged to the voltage of capacitors 22 and 23 (dotted line in FIG. 2), and then the collector-emitter voltage of transistors 2 and 13 is not equal to zero. However, with a constant delay t, - t, t, - t,

tg, t, - tg, it is possible to pick up capacitors 10 and 21 so that this voltage will be minimal or equal to zero and will not have a significant effect on the on and off processes.

 .

ten

Thus, the use of a fixed delay between cell key control pulses creates favorable conditions when the transistors are turned on and off, and the introduction of an additional phase shifter ensures that the voltage on the load is controlled without changing the output parameters of the converter.

Claims (1)

Invention Formula Constant voltage converter according to aut., Ev, no. 1257778, which is characterized by the fact that, in order to increase reliability by reducing the peak power dissipated in power transistors in transient modes, additionally introduced third and fourth inverter cells, similarly included, an additional control unit and a phase-shifting node, each control unit made according to the scheme with a fixed delay between the transistor control pulses of the inverter cells, the auxiliary output of the main control unit is connected to the control the input of the additional control unit through the phase-shifting unit, the control input of which is connected to the output of the converter, and the output windings of the transformers of the first and third, second and fourth inverter cells are connected in-series.