SU1363172A1 - Device for synchronizing computing system - Google Patents

Abstract

The invention relates to computing technology and can be used when building computing systems based on several digital computers of the same type. The aim of the invention is to reduce the sub-sync time. A distinctive feature of the device is that it allows shortening the subsynchronization time of the computing system by conducting a calibration mode with measurement of the generation time of control signals, taking into account the amount of asynchrony caused by instability of the master oscillator. The goal is achieved by the introduction of the comparison unit 5. 3 il. 35

Description

The invention relates to computing technology and can be used in the construction of computing systems based on several digital computers of the same type.

The purpose of the invention is to reduce the subsynchronization time.

FIG. 1 is a schematic of the device for synchronizing the computational effects of the first signal of exact time.

systems; in fig. 2 - time diagram of the device operation in the calibration mode; in fig. 3 - the same as in working mode.

The device contains a master generator 1, a counter 2, a register 3, a decipher 4, a comparison block 5, elements AND 6 of the first group 7, elements AND 8 of the second group 9, triggers 10 and 11, elements AND 12-14, an element OR 15, the input 16 of the asynchronous signal, the input 17 of the signal of the exact time of the total reference system and the outputs 18 of the device.

The device works as follows.

Driving generator 1 generates a series of clock pulses, which is fed to the counting input of counter 2. According to the states of the latter, at the outputs of the decoder 4, during operation of the device, (n-1) output signals are generated. In the operating mode of the computing system, the last (pth) signal of the control signal generation cycle is generated at the moment of comparison

SRI counter 2 and register 3,. when a signal appears at the output of comparator block 5.

The output signals 1,2 ... n-1, p through the outputs Ia of the device arrive at the control inputs of the computational engine of the computing system. When the last (n-1st) signal appears at the output of the OR 15 element, counter 2 is reset to O, i.e. transition to the next cycle of control signal generation. The number of control signals in the cycle is constant, i.e. is equal to p.

Elements AND 6 of group 7, triggers 10 and 11, and elements 12-14 control the calibration mode.

In the initial state, the triggers 10 and 1j are reset.

Consider the operation of the device when performing the typesetting mode on the timing diagram (Fig. 2).

At time t, (at the time of the occurrence of a nonsynchronous signal by

input 16) the signal arrives at a single input of the trigger 11. In this case, the trigger 11 is set to one state, the inverse output of which prohibits the generation of control signals at the outputs of elements And 8 of group 9.

At the moment of time

tj (during the change of the general reference system at the gate 17), the signal through the elements 14 and 13 goes to the single input of the trigger 10 and through the element OR 15 to the reset input in O of the counter 2, i.e. transition to the next cycle of control signal generation.

At time t4 (at the time

the second signal of the exact time of the total reference system on the input 17) the signal through the elements 14 and 12 is fed to the zero inputs of the flip-flops 10 and 11.

With this signal, the measured period between the two signals of the exact time of the total reference system in the clock pulses of the master oscillator 1 from counter 2 through the elements of Group 6 And 6 is rewritten to register 3 and stored there until the next calibration mode. The signal from the output of the element And 14 also goes through the element OR 15 to the reset input in O of counter 2, i.e. transition to the next cycle of control signal generation. The prohibition on the generation of control signals at the outputs of elements of group 8 of group 9 is removed. At this, the calibration mode is terminated.

During the calibration mode, the device uses only two consecutively received time signals from input 17, and the rest of the time these signals are not used.

Consider the operation of the device in

operating mode (Fig. 3).

In this mode, triggers 10 and 11 are cleared. According to the states of the counter 2, (n-1) output signals are generated at the outputs of the decoder 4.

At time t, -tg (the moment of comparison of the current value of counter 2 and the value on register 3 obtained in the calibration mode), at the output of the comparison unit 5, the n-th output signal is generated, which through element 8 of group 9 and element 15 enters reset input in About counter

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2, i.e. transition to the next cycle of control signal generation. The number of control signals in the cycle is constant, i.e. is equal to p. Output signals 1,2,.,., p-1, p through elements And 8 of group 9 and outputs 18 of the device arrive at the control inputs of the digital computer of the computing system .10

The mismatch of the last (nth) signal of the control signal generation cycle and the exact time signal of the total reference system, caused by the instability of the 15-pulse generator, is eliminated automatically without operator intervention.

Claims (1)

Invention Formula A device for synchronizing a computing system containing a master oscillator, a counter, a register, a decoder, two grythms of AND elements, two triggers, three AND elements, an OR element, the output of the master oscillator being connected to a counter input of the counter, the bit outputs of which are decoder and with the first inputs of elements AND of the first group, respectively, the outputs of the decoder are connected with the first to enter the corresponding elements AND from the first to (n-1) -th (where n is the number of device outputs) of the second group, output elements and the first to n-th second group are output to the first to nth apparatus, the output elements and the first to n-th first group are connected to the inputs Installations in 1 bit register 0 15 0 25 Q 40 724 Responsibly from the first to the fifth, the output of the OR element is connected to the reset input in O of the counter, the direct output of the first trigger is connected to the first input of the first element AND, the inverse output to the first input of the second element AND, the synchronization input of the device is one with the first input of the third element And, the output of which is connected to the second inputs of the first and second elements And, the direct output of the second trigger is connected to the third input of the second element And and the second input of the third element And, the inverse output of the second trigger is connected to the second inputs from the first to (n-1) -th element of the second group and with the first input of the n-th element of the second group, the output of the first element and connected to the zero inputs of the first and second flip-flops and the second inputs of the elements of the first group, output the second element I is connected to a single input of the first trigger, the input signal of the device non-synchronization is connected to a single input of the second trigger, characterized in that, in order to reduce the time of the asynchronization, a comparator unit is inserted into the device, and the counter outputs of the counter are connected respectively a first group of inputs of the comparison unit, a second group. the inputs of which are connected to the outputs of the register; the output is equal to the comparison unit connected to the second input of the nth element AND of the second group, the output of which is connected to the first input of the IL element, the second input of which is connected to the output of the third element I. tr 2 Phie. 2 j / 7 nr k1 / 7- / f /    f If, f I I h-J "O bWCTI AlTT JIILJ Lt J. P111 1111, GPI ILI 1   g Fi.Z Compiled by I.Safronov Editor M.Petrova Tehred LoIlyynyk Order 6362/39 Circulation - 671 Subscription VNISHI State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project) n, 4 t3 Proofreader V. But ha