SU1348826A1 - Device for adding binary numbers - Google Patents

Abstract

The invention relates to computing. The purpose of the invention is to expand the scope by forming a result in an arbitrarily chosen number system With a base. The device contains a register 1, accumulating adder 2, a group of I & W elements, a clock input 4, an L-ary counter 5, a delay element 6, and an encoder 7. 1 ip. i 1 (L with 4 00 00 N5 and

Description

The invention relates to computing.

The aim of the invention is to expand the scope by forming a result in an arbitrarily selected number system with a base L 2,

The drawing shows the block diagram of the device.

The device contains a register 1, accumulating adder 2, a group of elements And 3, a clock input 4, a counter 5 (L-EARNING), a delay element 6 and an encoder 7 that encrypts the binary code,

P (2 - L), where n is the register resolution 1;

k is an integer such that 2

The device works as follows.

Given a value, Tlj-at, applying a signal from input 4 to the inputs of the AND 3 elements, a binary number prerecorded in register 1 is transmitted to the inputs of accumulating adder 2, and the sum of the binary number recorded in register 1 and the numbers stored with the: / m-mat 2 before the clocking signal is applied. When the next signal arrives at input 4, the binary number of register 1 is added in the same way with the nova-i content of accumulating adder 2,

The overflow of accumulating adder 2, when the transfer signal is generated at the output of its older digit, the latter arrives at counter 5 (decimal) and simultaneously at delay element 6. Thus, the change per unit number recorded in decimal counter 5 corresponds to the registration of the transfer signal in the highest bit of accumulative adder 2, Considering that the transfer signal in the higher bit of accumulating adder 2 is formed when the latter is overflowed, the final result of the accumulation in decimal code for a fixed measurement time can be defined as the sum of the results obtained on a decimal counter 5 and accumulating adder 2, t, e,

S N 2 VM, (1)

where N is the number of counts of the decimal counter;

488262

M is the binary code of the residue stored in accumulator 2, after the end of the summation cycle.

As can be seen from this formula, the process of obtaining the final result of the summation in decimal code is associated with the multiplication operation, which is not always convenient 10,

To eliminate this drawback in the device, expression (1) is transformed using delay element 6 and encoder 7 into the following algorithm: .10 + M, (2)

where, 2 ,,, is a constant coefficient, the value of which depends on the number of bits of the accumulating adder 2,

In this formula, the term M equals

,, (2-10), (3)

where M is the binary number stored

in accumulative adder 2 25 after forming the transfer unit in the higher order; M, is the difference between the code of the number corresponding to the total capacity of the accumulating sum of 30 torus 2, and the closest number to a power of ten, the value of which is chosen less than decreasing. In expression (2) the multiplication process is greatly simplified due to the fact that each count is ten The actual counter 5 is a multiple of the selected number 10, In addition, in order for the multiple sum error Q to be minimal, the binary code of the difference M after the additional delay is again fed to the corresponding bits of accumulating adder 2,

Consider the operation of the proposed 45 device for summing, for example, a four-bit accumulating adder 2 and register 1, when it is necessary to repeatedly add the same binary code, for example,

35

code number 15. For this case, the total capacity of accumulating adder 2 and register 1 is 2 16, and the difference Mj for the coefficient k chosen in accordance with the previously specified condition, t, e,, is M (,

If the initial conditions are such that register 1 permanently contains the binary code of number 15, and accumulating adder 2 is zero, then when the first signal arrives at input A, the code of number 15 will be written into accumulating adder 2. When the second signal arrives at input 4, There is a summation of the code of the number 15 stored in accumulating adder 2, with the code of the same number received at the input of adder 2 after the second clock signal was applied. As a result of summation of these codes, the nojiy4eH binary code of the number 30, i.e. 11110. However, because accumulative adder 2 has four binary bits, the most significant bit of the code of the number 30 HP is recorded in the adder, and is used as a transfer signal for registration in the decimal counter 5 and simultaneously through the delay element 6 in the encoder. As a result, a binary code 1110 remains in the adpolator 2, i.e. The number 14. At 31 ohms, one adds to the contents of the decimal counter 5, which in the end result is a multiple of the number 10. By the same transfer signal, the delayed delay element 6, at a time slightly longer than the propagation time of the transfer signals in accumulation adder 2, the binary code of the difference M is formed, which in this case is equal to 6, i.e. the binary code is 0110. As a result, from the output of the encoder 7, the signals arrive at the inputs of the second. and the third bits of the accumulating adder 2. Thus, the code of the number 14 (1110) is added to the contents of the adder 2, the code of the number 6 (0110).

The unit of the highest bit of the binary code of the sum of these numbers, equal to 20 (code 10100), is recorded by the decimal counter 5 similarly to the above and is simultaneously used to form a difference code, the binary code of which is again fed to the accumulating adder 2, which is stored after forming the second carry in higher order code 0100, i.e. number 4.

As a result of such a twofold summation by the decimal 5, two transfer signals are registered, each of which is a multiple of 10, and the binary code of the number 10 is stored in the accumulator 2 as equal to

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with formula (3) the sum of numbers

ten

15

M 4 and.

Thus, the final value of the sum of the codes of two binary numbers 15 in accordance with formula (2) is equal to

S 240.

In the next operation, the summation of the input code of the binary number 15 with the remainder stored in accumulator 2 and equal to 10, decimal counter 5 will register another transfer signal, and the binary code of the remainder stored in accumulator adder 2 corresponds to The dc summation number 15, in which, a. Thus, the new value of the sum is

 -YU .

With repeated summation, when in formula (2) N-10 M, the value of the sum with a sufficient degree of accuracy can be represented as

 (four)

and the result of the summation can only be determined from the indications of the decimal counter 5.

Claims (1)

30 claims A device for summing binary numbers containing a register, a group of elements And accumulating a sum — a 2g torus and a counter, the outputs of the register bits being connected to the first inputs of the corresponding elements And groups whose second inputs are connected to the clocking input of the device. 2Q 25 40 and the outputs are connected to the inputs of the corresponding bits accumulating adder, the output transfer of the higher bit which is connected to the input of the counter, characterized in that, in order to expand the scope of application by forming a result in a randomly selected number system with a base, a delay element and an encoder are entered into the device, 5Q performs encryption into the binary code P (2 -L), where n is the register size, k is an integer such that P 0, L. 2, and the counter is L-ary, with the transfer output The 55th highest bit of the accumulating adder is connected via a delay element to the input of the encoder, the outputs of which are connected to the inputs of the accumulator of the accumulating adder.