SU1327267A1 - Shaper of signals with law-given phase change - Google Patents

Abstract

The invention relates to radio electronics and provides an increase in the accuracy of setting the law of phase change when extending the range of operating frequencies towards higher frequencies. The shaper contains a block 1 of form-one: Wani phase code, N converters 2 codes, reference generator (OG) 3, memory register 4, DAC 5, low pass filter 6, frequency divider 7, reversible counter 8 and switch 9. Clock to pulses received from exhaust gas 3 through frequency divider 7, block 1 generates a phase code t /, which is then converted into a code of sinusoidal functions in converters 2. According to switch 9, the reverse counting code 8 through switch 9 4 passes one of the converted signals. Depending on the value of the phase code i / formed by block 1, the device can perform the function of a phase shifter (at a constant value i), a frequency synthesizer (at a linearly varying phase) and a signal synthesizer (with a more false phase change law). The operation of block 1 is described. Blocks 7–9 and N-1 converters 2 are introduced. 4 Il. I (L sooo G5 FIG.

Description

The invention relates to electronics and can be used to generate signals with a predetermined phase change law, for example, in phase calibrators, frequency synthesizers, synthesizers with a polynomial frequency change law.

The purpose of the invention is to improve the accuracy of setting the law of phase change while expanding the range of operating frequencies towards high frequencies.

FIG. Figure 1 shows the structural electrical circuit of the proposed signal conditioner with a given law of phase change; in fig. 2 - diagrams of the system used source two-level signals; in fig. 3 - examples of the implementation of the phase code generation unit; figure 4 is an example of the implementation of the switch.

A signal conditioner with a predetermined phase change law contains a block 1 forming the phase code N of converters K9da 2, 2,. . , 2j, reference generator 3, memory register 4, digital-analogue converter (DAC 5, low-pass filter 6 (LPF), frequency divider 7, reversible counter 8, switch 9.

The phase code generation unit 1 (Fig. 3a) contains a dial pad 10 with N switches 11,. .., 1 1 j.

FIG. The ST is given a dial-up field 10 with N switches 1,. .., 1 Ij. and the drive 12 phase code.

FIG. Sv shows a dial-up field 10 with N switches 11 1 11, a drive 12 of a phase code, a drive 13 of a frequency code, an adder 14, a controlled inverter 15, Switch 9 contains M multiplexers 16.

A signal conditioner with a predetermined phase change law works as follows.

In each qM clock cycle of the reference oscillator 3n, an output of the frequency divider 7 with a division factor q gives rise to a pulse that arrives at the clock input of the phase code generation unit 1, the code output of which generates the phase code c, further to the inputs of converters 2., 2, .. , 2 | code that converts the phase code into a sinusoidal signal. At the output of the nth of N code converters, codes of sinusoidal functions are formed.

f sin {i / + 2Tr / N), (1)

five

which arrive at the corresponding signal inputs of the switch 9.

The principle of a signal former with a predetermined phase change is based on the fact that when summing up the periodic signals entering the N-phase system and multiplied by the corresponding sinusoidal functions of phase 1, also forming the Ijl-phase system, the result contains terms depending only on differences, or only on the sum of the full phases of the components of the periodic signal and the phase Any periodic signal without a constant component with frequency W can be written as a Fourier series

00

Up (t) V a sinku) t + b, coskLJt, (2)

In addition to (2), the N-phase signal system also includes signals

5 U (t) v (u) t + -JJ) -H

(u) t + -). (3)

The phase Lf corresponds to the N-phase system of trigonometric functions. The output signal

oo

I (t) - Ila, (kwt-4) + b ,, sin (kcot-t). (four)

When changing the sign before 2 / m / N, the difference () in (4) is replaced by the sum (wt + f).

. At a constant value of i, the device implementing algorithm (4) performs the function of a phase shifter, with

0 linearly varying phase - frequency synthesizer, with a more complex law of phase change - signal synthesizer.

The signal conditioner with a given phase change law (Fig. 1) uses discrete two-level signals (Fig. 2) as the N-phase system of the original periodic signals, the period of which is divided into

0 N equal intervals

0

u. (t)

  1 for (m + n) mod, O for other k.

(five)

where ... is the interval number;

() modN - operation of calculating the sum modulo N.

in the system of signals (5), at any moment of time, only one of the signals is different from zero (ie, equal to 1), which makes it possible to implement the algorithm (4), successively transmitting the corresponding N-phase system codes of sinusoidal phase functions (1) to the output .

The pulses of the reference generator 3 with a frequency N times greater than the required frequency uJ of the original periodic signals arrive at the counting input of the reversible counter 8 modulo N. The counting direction is determined by a signal at the installation input of the reversing counter 8 generated simultaneously with the phase code L ( in the phase code generation unit 1. The binary code of the number (t) modN from the output of the reversible counter 8 goes to the control input of the switch 9.

The output of the switch 9 in this case receives a code with tN- (m) of its signal input. A pulse from the output of the reference oscillator 3, which enters the clock input of the memory register 4, records the code from the output of the switch 9 into it, and a voltage proportional to the recorded code is generated at the output of the DAC 5. The LPF 6 transmits the first harmonic of the generated signal to the device output.

The entire bit of the grid of the block 1 of the formation of the phase code and the code converters 2, ..., 2 N is used for the implementation of the deviation of a given law of phase change from the linear corresponding to the carrier frequency. In this case, the phase code generation unit 1 and the code converters 2, .., 2fj operate at frequencies q / N times smaller than the carrier frequency, and the increase in the signal carrier frequency is accompanied by an increase in this ratio without increasing the operating frequency of the phase code generation unit 1 and converters code 2, ..., 2 ,.

The limiting operating frequency is determined practically only by the speed of the DAC 5.

The phase code generation unit 1, using the proposed signal conditioner with a predetermined phase change law as a phase shifter, can be performed, for example, as a keypad 10 with N switches 11, ..., 1 1 .J (Fig. 3a) two positions in one of the

.

ten

20

327267.

On the corresponding output of block 1, the signal O passes, and in the other - 1. The position of the switches 11 ;,,. . ., 1 1 kj dial pad 10, it is possible to generate different phase codes.

The phase code generation unit 1, when using the device as a frequency synthesizer, can be performed on the basis of the accumulator 12 of the phase code (FIG. 36). With each clock pulse, the code set on the dial pad is added to the code recorded in the accumulator of the code for phase 12.

.g 105 as a result of which a linearly increasing phase code is formed at the output, corresponding to the desired deviation of the frequency of the signal being formed from the frequency of the original signal. The signal about the sign of the deviation comes from the corresponding of the 1 C, ..., 1 1 switches of the dial-up field 10 to the output of the control signal of the operating mode of the reversible counter 8 block 2g of 1 forming the phase code, min drive 12 of the phase code.

When using a signal generator with a predetermined phase change law as a signal synthesizer, a linearly varying frequency code is formed in frequency generator 13, which is part of the phase code generation block. This code is summed with the initial frequency code received from the dial-up unit of 35 l 10 in the adder 14. In the phase code accumulator 12, the phase-modulated linear frequency (LFM) signal is generated, which is parabolicly variable. In this case, the signal from the higher bit of the adder 14 is fed to the control input of the controlled inverter 15. The same output of the adder 14 is the output of the reverse mode control signal

45 counter 8 of block 1 of the formation of the phase code. If at the signal O in this bit, the remaining bits of the phase code are inverted by the controlled inverter 15 and

50 reverse counting mode

thirty

40

ka 8, and at signal 1 - direct transmission and subtraction mode, respectively, then in such a device the increasing law of linear 55 frequency modulation is realized. In order to obtain a falling law, it is necessary, with a signal O in the highest bit of the adder 14, to ensure the direct passage of the remaining bits through the controlled one.

1327267

the inverter 15 and the subtraction mode of the reversible counter 8, and at the signal 1, the inversion and addition mode, respectively.

Converters of code 2, ..., 2 can be, for example, implemented on the basis of permanent storage. devices of the corresponding volume or in the form of a logical structure. For even N, N / 2 function codes can be obtained by inverting other N / 2 codes.

The switch 9 can be made as a parallel connection of the required number M of multiplexers, and the number M is equal to the number of code bits of each sinusoidal function.

score1; 1st input is connected to

Claims (1)

Formula iso.b re shadow the output of the reference generator, the setup input - with the output of the signal controller signal generator with the specified Q control mode of the reversible law of phase change, containing the counter of the code generation unit, the phase code generation unit, the code segment, and the output with the control input with the input of the pre-switch, between the output of the code generator, the sequential reference oscillator and the clock input-connected memory register, the digital code of the phase code generation unit, the log converter and F1-pin are lower is led frequency divider. These frequencies, as well as the reference oscillator, the output, which is connected to the clock input of the memory register, is characterized in that, in order to improve the accuracy of setting the law of phase change when extending the operating frequency range towards high frequencies, (N-1) code converters, whose inputs are connected to the code output of the phase code generation unit, the switch, each of the signal inputs of which is connected to the output of the corresponding N code converters, and the output is connected to the memory input of the memory register, roar rsivny by chik, score1; 1st input is connected to FIG. g R FIG 3 IfH / n. Sxosbi R / A, -, fzg if Compiled by G. Zakharchenko Editor M. Tovtin Tehred V. Kadar 3407/54 Circulation 901 Subscription BNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, - Uzhgorod, st. Project, 4 four Code Proofreader B. But ha