SU1317456A2 - Device for determining characteristics of random processes - Google Patents

Abstract

The invention relates to the specialized means of calculating techniques for determining the statistical characteristics of random processes, in particular the definition of quantiles, and is additional to the author. No. 1043665. The purpose of this invention is to improve accuracy. The device contains a buffer memory register, a pulse generator, switches, a register, switches, counters, blocks read; n, large-scale amplifiers, adders, element, delays, AND groups, integrating chains, registration elements, output groups, error analysis block having a specific design for a given device. The invention consists in identifying anomalous results, measurements and excluding them from the sample used to determine quantiles. The device can be used in systems for statistical processing in any kind of scientific research. 3 il. with S cl DO 1 4 SP 05

Description

I1

The invention relates to specialized means of computing and can be used in determining the statistical characteristics of random variables, namely, to determine quantiles, and is a further development of the device according to Aut. No. 1043665.

The purpose of the invention is to demonstrate the accuracy of the device.

Fig, 1 shows a block diagram of the proposed device; FIG. 2 is a block diagram of an error analysis block; on fig.Z - structural scheme of the distributor of output signals,

The device for determining the characteristics of a random process contains (FIG. 1) a buffer memory register 1, a pulse generator 2, switches 3, register A, the first switch 5, counter 6, pulses 5 and a counter. 7 number of inversions, comparison circuit 8, second switch 9, element group AND 10, subtraction blocks 1, scale amplifiers 12, adders 13, device outputs 14 for quantile determination, counter 15 cycles, delay element 16, elements 17-20 , block 2 error analysis distributor 22 output signals of the device outputs 23-25.

The error analysis block 21 (FIG. 2) contains a key 26p register 27, the first reader 28 quadrtor 29, averaging Yush; i (non-recursive) filter 30, 3 pulse generator, averaging (non-recursive) filter 32e first element I 33, first the delay element 3.4, the second element AND 355 pulse counter 36, the third element AND 37., the second subtractor 38, the first divider 39 of the code; the root extraction unit 40, the fourth element And 41, the third subtractor 42, the second divider 43p of the first Comparison element 44, the second element 45 of the comparison, the element OR 469 the element NOT 47, the fifth element AND 48, the second element nt 49 delay, the third element 50 delay, the second element is NOT 51, the test element And 52, the seventh element And 53, the eighth element And 54,

Distributor (fig.Z) output signals. contains the first group of elements And 55, the second group of elements And 56, the third group of elements And 57, the fourth group of elements And 58,

7456 2

The device implements the following algorithm for determining quantiles.

At its input comes a sequence of independent samples, from .5 of which the device periodically takes a sample of -N values (x, x ,,,, (X) and rearranges it into a variational series in accordance with the condition

five

0

five

 oi -l- - cn

   ((H) (

where (L) l5N is the number of the sample member in the ranked row ,.

The value of quantile j, refined with interpolation, corresponding to a given probability level P, is determined from

X,.,. (k ...... - X (.; .. j .U.J

(i)) -j + i

+ X

(2)

five

L (o,

where (i) j P (NH-I) is the number of the sample member with the required quantile;

t is a fraction of a prisoner number; AJ () i (clarifying amount

interpolations; j is a subindex indicating the level of probability for which the quantile is determined,

At the same time, selective sampling is determined for the sample.

40

  N

(3)

standard deviation

g

45 S .i (x; - 5)

   .

(four)

statistics

50

(five)

statistics

(6)

IS

and verifying the condition

T, C. (7)

T, C, (8)

where C is a criterion with given level of significance oi and confidence probability p (P t, - p; l 1 – p).

When (7) and (8) are not fulfilled, then in accordance with (2) the quantile values sought are received in their group of outputs for use. If (7) or (8) or simultaneously (7) and (8) are satisfied, then the x,, or x., Or

simultaneously x

1U

and X

(ABOUT

not used because they are considered abnormal observations.

In these situations, the values of the sought-for quantiles are in accordance with (2) with regard to reducing the sample size by 1 in the cases of (7) or (8) and by 2 in the case of simultaneous values (7) and (8), and For each case separately in their groups of exams.

The algorithm is implemented in the device as follows.

The input of register 1 of the buffer memory receives a sequence of independent samples. Register 1 of the buffer memory after filling the signal into the pulse generator 2. According to this signal, the generator of 2 pulses gives a 4-packet of N pulses to the clock input of the register. Under the influence of clock pulses, the sequence values from the register 1 of the buffer memory are sequentially received. Through the information input into register 4 with the volume of N bits. Thus, in the main register 4, a random selection of values is formed

(h. ,,

fx. i

2

The clock frequency is selected in such a way as to match the rate at which the original sequence arrives at the input of register 1 of the buffer memory with the speed at which the sample is written to register 4 and the speed at which it is processed. The sampling values simultaneously with the recording in register 4 through the information outputs of each register bit 4 are set at their respective inputs of the first switch 5, switches 3 and their corresponding inputs of each of elements 10 AND of the group.

The generator of 2 pulses, having completed the delivery of a packet of N clock pulses, begins to increase a continuous sequence of sync pulses, which occur on the synchronous inputs of the commutator 5

50

Ditch 5, 9 and to the input of the counter 6 pulses.

In time with the sync pulses, the procedure of ordering (ranking) the sample begins:

The ranking procedure is based on a pairwise permutation algorithm. On first viewing, each sample value X, - is compared with the neighboring value. X, -,. A pair of values whose samples have the inequality x - X. changes places.

Pairwise comparison and rearrangement of the members of the sample continues until the sampling ranking process, t, e,

(,))) - (m) V The fact of fulfilling the inequality x, +1 P the pairwise viewing of the preset is the inversion, and the function of the sum of inversions is determined by the expression

W-1

 Z: v (x., X- ,,)

(9)

Where

1, X; X

1 + 1

5 o 5

0

- P

V (x ,, x. ,,)

O, X; i X

441

The value is calculated during each cycle of pairwise comparison and permutations of the members of the sample. A sign of the end of the sampling ranking is the value of t, counted per cycle of viewing.

In the device ranking proiz. is as follows

In each viewing cycle, the switch 5, in sync with the clock pulses, sequentially connects the information outputs of each adjacent pair of register bits 4 to the two inputs of the comparison circuit 8. As a result of the comparison of each pair of neighboring sampling members, the comparison circuit 8 outputs the inversion value V (x, x ;,) as O or 1. These values are fed into the counter 7 of the number of inversions, which in accordance with expression (9) determines the sum of inversions 1 for each cycle of viewing, at the same time each value of the inversion is fed to the input of the switch 9,

Work synchronously with the switch 5, the switch 9 in series

It is connected to the output of circuit 8 against B: the switch of the switch Zz which, with its other two inputs and two outputs, is connected respectively to the information outputs and information inputs of each of the pair of register bits 4, the contents of which are analyzed by the circuit 8 of comparison. At the same time, switch 9, in order not to complicate the design of switches 3. converts the value V (, x) 0 to its input at its output - 1, leaving the value V (x;, x ,,,) 1 unchanged.

Switch 3 connects the information outputs connected to it of a compared pair of adjacent bits with its outputs so that when V (x, -5X.,) O at the input of switch 9, the contents of the register bits being compared remain unchanged and when V (xj, x .) 1 changed places by; rewriting from one bit to another, then switch 3 returns to the neutral position,

The end of each viewing cycle is determined by a 6-pulse counter and a 15-cycle counter. In the first viewing cycle, the 6-pulse counter counts the N-1 pulse from a sequence of sync pulses received at its input from the 2-pulse generator (N-sample size) ,: This determines the boundary of the first cycle. As a result, a one-time pairwise comparison and rearrangement is carried out in accordance with the accepted algorithm of all the members of the sample, containing B-register 4,.

If at the same time the cycle of the counter 7 of the number of inversions receives C 5, then the transition to the second cycle of viewing is performed, the potential of the generator of the 2 pulses and the group of elements And 10 from the output of the counter of the 7 number of inversions does not change. Therefore, the pulse generator 2 continues to generate a sequence of clock pulses to control the switches 5 and 9, and the PA elements 10 still remain locked. The counter 6 is pulse-matched law-chpv counting up to N-1, with its output signal it resets the counter 7 of the number of inversions to its initial state and returns to the initial state. switches 5 and 9, the next viewing cycle begins with the same register bits, 4. At the same time, the counter of 6 pulses writes 1 to the counter of 15 cycles.

The amount from the counter of 15 cycles (in this case, 1) goes to the second. This is the input of the counter of 6 pulses, where it reads from the set number written there, to which the counter of 6 pulses must read. As a result, the number of pairwise comparisons of the sample members in the second scan cycle is reduced by 1, to

5 N-2, and the largest member of the sample in the ranked row, which already occupied the extreme place in the first viewing cycle, does not accept participation in pairwise comparison in the second and subsequent viewing cycles, since switches 5 and 9 are produced before returning fewer switchings to initial positions,

The scans of viewing with decreasing chi ate of pairwise comparisons by 1 in each successive cycle are continued until the condition is satisfied. When G, the counter 7 of the number of inversions stops in -g, the clock generator generator 2

0 pulses., Resets the counter of 15 cycles to the initial state and unlocks the elements of AND 10. This moment corresponds to the formation of the ranked sampling at the inputs of the elements AND 10

(Xf ,,, 7.) (%)

Simultaneously with the ranking of the sampling value of the sample from the information output of the register 1 buffer

The Q memory goes to the error analysis block 21 (FIG. 2) at the input of the averaging south filter 32 and at the information input of the register 27. The filter 32 operates in the averaging mode and ensures that you calculate the mean value: x in accordance with (3), Register 27 due to the receipt of its clock input through the switch 26 packs of N pulses from the clock output of the generator 2

Q pulses produces a sequential record of the X, g X,,,, X HJ values received by it,

A pack of N clock pulses is also fed to the information input g of the counter 36 pulses. Considering N pulses, which means that the calculated value of x appeared at the output of the second filter 32, and all the values of the sample are written in register 27,

the pulse counter 36 outputs a pulse, which is fed to the control input of the switch 26, to the start input of the pulse generator 31, to the input of the first AND 33 element, to the input of the first delay element 34 and to the reset input of the counter 36.

On this signal, the generator 31 generates a burst of N pulses, which through the switched key 26 arrive at the clock input of the register 27, reading from it the recorded values of the sample. These values are successively fed to one of the inputs of the subtractor 28, to the other input of which, through the opened first element AND 33, from the output of the filter 32, the value X is supplied. Simultaneously, X is fed to one of the inputs of the second subtractor 38 and the third subtractor 42.

Subtractor 28 executes one

X.-X, the result of which passes the quadrant 29 and being squared there enters the input

JO

The unit is 43, where, in accordance with (6), T is determined. The value of T is fed to one of the inputs of the second comparison element 45.

Through the second inputs, the constant value C is pre-entered into the comparison elements 44 and 45. The performance is checked in these elements. conditions in accordance with (8) and (7). In the case of simultaneous fulfillment of conditions (B) and (7), which means that the anomaly is both X (X) and x, |, j, the output signals of both circuits appear at the outputs of both circuits

15, the respective inputs of the element OR 46, the fifth element AND 48, the second delay element 49 and the third delay element 50.

The resolving signal from the output of the element OR 46 is converted by the element HE 51 into a creaking and locks the traditional eighth element AND 54. The resolving signal from the output of the fifth element And 48 turns into an elementary (non-recursive) filter with the HE 47 into the choking and locks 30, which computes the seventh element And 53 and the eighth element And 54. Locking the element And 53 and the element And 54 due to the presence of ele-2

- 2.

  Jt i - / h

S - (x, -x)

thirty

 the delay element 49 and the element 50 per pulse from the output of the counter 36, delayed by the delay element 34 by the time required to form the filter 30 S on the filter, opens the second element And 35 and the value S

The holders pass earlier than the resolution signals from the outputs of the latter usually pass through the opening of the sixth element AND 52 and the eighth element And 54, respectively, and in TC at their outputs. through the element And 35 enters the block

40. extracting the root, where S is determined according to (4). This value goes to one of the inputs, divider 39 and divider 43. at 0

The output signal of the counter 7 of the number of inversions, indicates the end of the ranking, opens the third element And 37 and the fourth element AND with a group of prescriptions device41. Values,., Of the digit and .45 o „„ „....

Thus in the case of simultaneous anomaly x ,,. , х / j, i only at the output of the fifth element AND 48 of the analysis unit 21, according to a Vits permitting signal, which will go to the second registration element 18 and to the distributor 22 (FIG. 3) to the first inputs of the second group of I56 elements, whose outputs 24 (M x, from the 1st bit of register 2 respectively; respectively, through the open third element And 37 and the fourth element And 41 post to the second inputs of the subtractors 38 and 42.

50

va. The registration element can be made in the form of, for example, a light panel indicating the number of the group of outputs of the device through which information is given and about the anomaly of one or another sign. sampling.

X difference

(TO)

-X from the second subtraction

(O R the receiver 38 is fed to the second input, the strobe signal appears only on the divider 39, where T is determined at the output of the second comparison element 45 according to (5). The value of T, the next 5th Element OR 4b and the element

NOT 51 also locks the eighth element And 54. At the same time, due to the fact that the fifth element And 48 is locked at one of the inputs of the second element, 45 of the comparison.

The difference xx from the subtractor 42 enters ..to the second input of the second one to the input, allowing the signal about O

The unit is 43, where, in accordance with (6), T is determined. The value of T is fed to one of the inputs of the second comparison element 45.

Through the second inputs, the constant value C is pre-entered into the comparison elements 44 and 45. The performance is checked in these elements. conditions in accordance with (8) and (7). In the case of simultaneous fulfillment of conditions (B) and (7), which means that the anomaly is both X (X) and x, |, j, the output signals of both circuits appear at the outputs of both circuits

5, the respective inputs of the element OR 46, the fifth element AND 48, the second delay element 49 and the third delay element 50.

The enable signal from the output of the element OR 46 is converted by the element HE 51 into a crackling and locks the conventional eighth element AND 54. The enabling signal from the output of the fifth element And 48 turns into the HE 47 into a crackling and locks the seventh element And 53 and the eighth element And 54. Locking element And 53 and element And 54 due to the presence of elect30

 The delay element 49 and the delay element 50 pass before the permitting signals from the outputs of the latter usually pass through the opening of the sixth element AND 52 and the eighth element 54, respectively, and at their outputs 35.

The holders pass earlier than the permitting signals from the outputs of the latter usually open, respectively, the sixth element And 52 and the eighth element And 54 and in TC at their outputs.

  In the case of a simultaneous anomaly x ,,. , х / j, i only at the output of the fifth element AND 48 of the analysis unit 21, according to a Vits permitting signal, which will go to the second registration element 18 and to the distributor 22 (FIG. 3) to the first inputs of the second group of I56 elements, whose outputs 24 about" "" ....

va. The registration element can be made in the form of, for example, a light panel indicating the number of the group of outputs of the device through which information is given and about the anomaly of one or another sign. sampling.

In the case of anomaly x.

(O P r zreromu input, permitting signal pro913

A second delay element 49, the seventh element I-53, walks and appears at the output of the last one. Then it goes to the first registration element 17 and to the distributor 22 to the first inputs of the first group of elements And 55 whose outputs 23 are the first group of outputs of the device,

In the case of the anomaly x,.,. analo1 1

befitting the occasion with x

U)

remains closed

the sixth element And 52, and the enabling signal from the output of the second comparison element 45, having passed the third delay element 50, and the eighth element 54, appears at the output of the latter. Then it nocTjmaeT into the third registration element 19 and into the distributor 22 to the first inputs of the third group of elements 57, outputs 25 of which are with the third group of outputs of the device,

If there are no anomalous observations, the signals at the outputs of the comparison elements 44 and 45 are missing the sixth element AND 52 remains open and the signal from the inverter number counter 7 indicates the end of the ranking J delayed by the delay element 16 for the time required to detect the anomalous observations And 52, from there to the fourth registration element 20 and to the distributor 22 to the first inputs of the fourth group of elements And 58, the outputs 14 are the fourth group of device outputs

From the group of open elements And 10, the values of the members of the ranked sample come to the distributor 22, where, being divided into four groups in accordance with the situations considered (Figs. 3, 4a, b, c, d, e), are sent to the second inputs according to the algorithm for determining quantiles in each group, some of the values go to the second inputs: their corresponding AND elements of their group directly from the outputs of the AND 10 element group, and some through interpolation chains.

Interpolating the quantil value that is sought is performed in accordance with (2) as follows,

Information from And 10 elements with previously known numbers (i) jj, (i) + 1 goes to the first and second inputs respectively

vuem.im block 11 subtraction. In addition, information from the output of the element And 10 with the number (i); simultaneously arrives at one of the inputs of the adder 13, which is included in the same interpolation chain. In subtractor block I1, the difference X | - is determined. - -Hg,;, .-, entering the large-scale, amplifier 12, included in this interpolation chain.

In the master amplifier 12, the received difference is multiplied by the previously known interpolation fraction L:. The product from the scale amplifier 12 is fed to the second input of the adder 13, where finally, in accordance with (2), the value of the desired quantile, refined by interpolation, is obtained

So at the second entrances

Each of the four groups of elements forms a complete set of the quantiles sought, corresponding to this group, i.e. situations when X is dropped

(Ml

simultaneously x

((

and X nij or abnormal observations are missing. However, only one

0 a set of quantiles, for which the resolving signal came to the first inputs of one of the groups of elements And from block 2 of the analysis in accordance with the specific situation existing

,; .tl this sample. At the same time. the registration element indicates the availability of information B to a specific group of conclusions. After the information has been retrieved, the process is repeated for new sampling values.

Claims (1)

Invention Formula A device for determining the characteristics of a random process according to the author. Ev. No. 1043665, characterized in that, in order to improve accuracy, a delay element, an additional three groups e of n integrating chains and an additional four groups of elements And, outputs of elements And which are outputs of the corresponding quantiles of the random process , the first inputs of the elements AND of each executive group are connected respectively to the outputs of the integrating chains of their group, an error analysis block consisting of a key, generation 11: 1 the pulse torus, EI elements, OR element, pefHCTpa, three delay elements, two NOT elements, pulse counter, three subtractors, TWO averaging filters, a quad, a square root extractor, two code dividers and two comparison elements, an output the pulse counter of the error analysis block is connected to the first input of the first element I, the input of the first delay element of the error analysis block, to the start input of the pulse generator of the error analysis block and to the control input of the key, whose information input is connected to the output ohm of the pulse generator of the error analysis block, and the output of the key of the error analysis block is connected to the clock input of the register, the output of which is connected to the first input of the first subtractor, the second input of which is connected to the output of the first element I, and the output of the first subtractor through a series-connected quadrant and first averaging the filter is connected to the first input of the second element And, the second input of which is connected to the output of the first delay element, the reset input and the high-order output of the pulse counter of the error analysis block are connected the input of the second averaging filter and the information input of the error analysis block register are connected to the output of the buffer memory register, and the information input of the pulse counter of the error analysis block and the first information input of the key of the error analysis block are connected to the first output of the device pulse generator filter is connected to the second input of the first element And, to the first inputs of the second and third subtractors, respectively, the second inputs of which are connected respectively to the outputs of the third and fourth on the elements and, as the second and third v1hody vychita612 telephones are connected to the first inputs of the first and second code dividers, respectively, the second inputs of which are connected to the output of the extraction unit the square root and the divider codes of the code dividers are connected to the first inputs of the first and second comparison elements, respectively, the second inputs of which are the input of the device constant, the output of the first comparison element of the error analysis block is connected to the input of the second delay element, the first inputs of the fifth And element and the OR, the output of the second reference element is connected to the input of the third delay element and to the second inputs of the fifth AND element and the OR element, the output of which through the first element is NOT connected to the first the input of the sixth element And the second. the input of which is connected to the output of the delay element of the device, and the input of the delay element of the device is combined with the first inputs of the third and the fourth element AND the analysis unit and is connected to the output of the count of iversions, the output of the fifth element AND, the analysis unit through the second element is NOT connected to the first inputs, respectively. of the seventh and eighth elements And, the second inputs of which are connected respectively to the outputs of the second and third elements of the delay, the second input of the third element I is connected to the output of the high bit register of the device, and the second input of the fourth element I is connected to the output of the first bit the device register, the outputs, the fifth, the eighth and sixth elements AND the error analysis block are connected respectively to the first inputs., And, respectively. the first, second, third and fourth elements of the elements, e. The inputs n of the integrating circuit with each additional group are connected respectively to the outputs of the elements AND groups of the device. ( tl4..t n ... t ft .. -1 It .. .t one r-% 1 p-n G-1 rO,  "N4 Llfrj ij Lj W, $ T. iIlZIlJ five 5C s "Sj ff  I I I I I I I CS) f "Ni Cofjsi OTH (tsl. 3 . sixteen  Norm Excl. X (il I fiCM. X (N} CpU2.2 Qbl.22 22 Compiled by E. Sechin Editor N. Gorvat Tehred V. KadarKorrektor M, Demchik Order 2426/45 Circulation 672 Subscription BHfiPniI I USSR State Committee for Inventions and Discoveries-. 113035, Moscow, Zh-355. Rauushsk Nab ,, d / 5 Production and Polygraphic Enterprise, Uzhgorod, st. Project, 4