SU1300465A1 - Device for extracting square root - Google Patents

Abstract

The invention relates to computing and can be used as a functional expander in large computers or autonomously as a specialized calculator in calculating the characteristics of random processes. The aim of the invention is to improve the accuracy of calculations by obtaining the fractional part of the result. The device contains a clock pulse generator 1, the first element And 2, the trigger 3, the divider 4 frequencies into two. Zapum, (L

Description

the first integrator 5, the second integrator 6 the third integrator 7, the first comparison circuit 8, the second comparison circuit 9, block 10 summation and subtraction, delay element 11, first el:; ment OR 12, second element OR 13, second element AND 14 , frequency divider 15 by five, third ele

The invention relates to computing and can be used in specialized computers in measuring the characteristics of random processes.

The purpose of the invention is to improve the accuracy of calculations by allowing the fractional part of the result to be obtained.

Figure 1 shows the functional diagram of the device; Fig. 2 illustrates a frequency divider. with a variable division factor, an example of execution; FIG. 3 shows a summation and subtraction unit, an example of execution.

The device for extracting the square root contains a generator of 1 clock pulses, the first element AND 2, the trigger 3, the divider 4 frequencies into two first 5, second 6 and third 7 integrators, first 8 and second 9 comparison circuits, unit 10 summation and subtraction, element 11 delays, the first 12 and the second 1J elements OR, the second element AND 14, the frequency divider 15 by five, the third element OR 16, the third element AND 17, the frequency divider 18 with a variable division factor, and the control block 19.

The control unit 19 includes the first element OR 20, the first trigger 21, the second element OR 22, the first element AND 23, the second trigger 24, the third trigger 25, the second element AND 26, the fourth trigger 27, the first 28 and the second 29 pulse shapers, the third the element OR 30, the fifth trigger 31, and the third element AND 32.

The device operates as follows.

ment OR 16, third element AND 17, frequency divider 18 with variable division factor, control block 19. The calculation of the square root is carried out sequentially: the calculation of the whole part and the calculation of the fractional part. 3 il.

The result of the square root extraction is determined by the expression:

N + - 10

INiiN ".ll5

 NK - processed number

N is the closest to N chicJIo, the root of which is an integer.

The fractional part of the expression has a + sign when the value of the 5gh processed number

15

NXU NX N,

"and,

and sign - at the values of the processed number

NXU - (O N, N,,

First, the integer part of the result -JN ,, is calculated. All device integrators are set to the zero state by a pulse, the duration of which exceeds the transient time in the circuit. Impulse Start - sets the triggers 21 and 25 to the zero state. The low level signal from the output of the flip-flop 25 is applied to the element AND 32, prohibiting the passage of the output pulses of the comparison circuit 8 during the calculation of the integer part of the result. From the inverse output of the flip-flop 21, the signal arrives at the element AND 2. With the arrival of the impulse the trigger is entered into the integrator 5, the trigger 3 is set to the zero state, giving an enable signal, the signal to the element 2, the element 2 and opens, and to integrators 6 and 7 pulses of frequency t and f pass, respectively. With equal pulses in the integrators 5 and 6, the comparison circuit 8 operates, the output pulse of which sets the trigger 3 to one state and resets the integrator 6 to the zero state. The passage of pulses through the element 2 is stopped. The output impulse of the comparison circuit 8, having passed through the delay element 11, after a time c expires, returns trigger 3 to the zero state and writes the next unit to integrator 5. From this point on, the described device operation cycle repeats. When it is achieved, then, when working with the device, two cases are possible.

If in the process of subtraction, the inter- rutor 7 does not go through O, it takes place at the values of the processed number

NXU N, N

hc

KU,

ten

then with the equality of the pulses in the interiors 5 and 6, the comparison circuit is triggered, the decoded pulse of which translates the leading edge of the trigger 21 into a single state, and the rear

the number of pulses in the integra 5 front — trigger 24 per unit 7 to the processed number N is triggered by comparison circuit 9, according to the output pulse of which the block part of the result is fixed in block 10 of addition and subtraction, in division 18 with a variable division factor the coefficient division equal to ,,, and integrator 7

25

thirty

|| USHP,

is reset to the zero state. The output pulse of the comparison circuit 9 sets the front edge of the counting trigger 25 to one state, passes through the AND 26 element and the OR 22 element, sets the trigger 21 to the single state. The high level signal from the output of the trigger 25 goes to the element AND 32, allowing passage of the output pulse of the comparison circuit 8 during the calculation of the fractional part of the result. From the zero output of the trigger 21, a signal is given that prohibits the passage of the counting pulses through the element 2. A pulse passed through the 26 And the trailing edge triggers the one-shot 40, the output of which permits recording to integrator 7 of the contents of integrator 5 via the element 17, the falling edge of the output signal of the one-shot 28 triggers the one-shot 29, o the single signal of which through the element OR 30 sets the trigger 31 to the one state, and through the element OR 20 to the trigger 21 to the zero state. From the zero output of the trigger 31, the signal transfers the integrator 7 to the subtraction mode, and from the zero output of the trigger 21, the signal permits the passage of counting pulses through the element 2, and the integrator 6 and 7. From the zero output, three times a signal is received, prohibiting the passage of pulses through ale II. In the integrator 7, the Nj-N tatsk is detected. From the single output of the trigger 24, a signal arrives that interrupts the passage of the counting pulses through the element 14, and a number equal to the integrator 7 and the divider 18 are given to the input of the device;

f, respectively. At the moment 7

T

The integrator / state is triggered by the comparison circuit 9. Next, the trigger 24 goes into zero state, prohibiting the passage of pulses through the element And 14. In d 35 the body 18 of the frequency with a variable division factor fixed core on the part of the result

.

 Yu

lNjLl Nit5.) 5

Ji

hc

45

55

which is summed up in block 10 of averaging and subtraction with integer parts of kg. The result of the quadratic root extraction is output to the device.

If during the subtraction the integrator 7 goes through O, which is the case when the value of the processed number is

"Hc - (- .N,,

then the output pulse of the integrator 7 sets the triggers 27 and 31 of the control unit to the zero state. From the trigger output 31, the high-level signal converts the integrator 7 into the summation mode, and from the trigger 27 output, the low-level signal translates

stroke t pulses of frequency g and f

Responsibly, Next, when the device is operated, two cases are possible.

If in the process of subtraction, integrator 7 does not go through O, which is the case for the values of the processed number

NXU N, N

hc

KU,

then, with equal pulses in the integrators 5 and 6, the comparison circuit 8 is triggered, the spin code of which converts the trigger edge 21 into a single state, and the rear edge

front - trigger 24 in a single

front - trigger 24 in a single

condition. From the zero output of flip-flop 21, a signal is received that prohibits the passage of pulses through element 2. In the integrator 7, the rest Nj-N is recorded. From the single output of the trigger 24, a signal is received permitting the passage of the counting pulses through the element 14, and a number equal to zero is applied to the input of the device. The integrator 7 and the frequency divider 18 with a variable division factor receive pulses of frequency

f, respectively. At the time of completion, 7

T

The integrator / state is triggered by the comparison circuit 9. In this case, the trigger 24 goes into the zero state, prohibiting the passage of pulses through the element 14. In the frequency division 18, the fractional part of the result is fixed with a variable division factor 18

lNjLl Nit5.) 5

Ji

hc

tall 21 sharp a- 40 ovo - 50 dir45

55

The code is summed up in block 10, the summation and subtraction, with an integer portion of kg. The result of extracting the square root. Comes to the output of the device.

If in the process of subtraction, the transition of the integrator 7 through O occurs, which is the case for the values of the processed number

"Hc - (- .N,,

then the output pulse of the integrator 7 sets the triggers 27 and 31 of the control unit 19 to the zero state. From the output of the trigger 31, the high level signal switches the integrator 7 to the summation mode, and from the output of the trigger 27, the low signal translates the fO

The unit 10 is the summation and subtraction in subtraction mode. If the pulses in integrators 5 and 6 are equal, the comparison circuit 8 is triggered, the output pulse of which converts the leading edge trigger 21 to the unit state, the trigger 31 to the zero state, and the falling front to trigger one 24, From the zero output of the trigger 21 a signal is received that prohibits the passage of pulses through an AND 2 element. In the integrator 7, a residual is fixed. A low level signal arrives from the output of trigger 31, translating integrator 7 into subtraction mode. A single output of the trigger 24 receives a signal, permits the passage of the counting pulses through the element 14, and the input of the device is given a number 0 equal to zero, the integrator 7 and the divider 18 receives pulses of frequency f

15

-5-and

f respectively, At the moment

25

when the integrator reaches the 7th state, the comparison circuit 9 operates. In this case, the trigger 24 goes into the zero state, prohibiting the passage of pulses through the element 14, In the frequency divider 18 with a variable division factor, the fractional part of the result is fixed

which is subtracted in summation and subtraction unit 10 from the integer part. The result of extracting the square root is fed to the output of the device.

Claims (1)

Invention Formula A device for extracting the square root, containing a clock pulse generator, three integrators, two circuitry schemes, two OR elements, a summation and subtraction unit, a frequency divider by two, a trigger, the first AND element, and a delay element, and the device start input is connected to the first the inputs of the first and second elements OR, the second inputs of which are connected to the output of the delay element, the input of which is connected to the installation input of the first trigger, the reset input of which is connected to the output of the first element OR, the inverse output of the trigger and a generator output 0 five clock pulses are connected respectively to the first and second inputs of the element I, the output of which is connected to the input of the frequency divider into two, the outputs of the second element OR and the frequency divider into two are connected to the information inputs of the first and second integrators respectively, the information outputs of which are connected to the first and second information the inputs of the first comparison circuit, the output of the attribute being equal to which is connected to the reset input of the second integrator and to the input of the delay element, the information output of the first integrator nen to a first data input of summing and subtracting unit, whose output is the output of the result strobiruyuschny input of summing block and the subtractor output is connected to the second circuit is equal to the characteristic Cf. The first and second information inputs of which are connected to the input argument of the device and to the information output of the third integrator, respectively, so that, in order to improve the accuracy of calculations by ensuring the possibility of obtaining the fractional part of the result, a frequency divider with a variable division factor, a frequency divider by five, a second and The third AND elements, the third OR element, and the control block containing five triggers, three OR elements, three AND elements, two pulse formers, and the device start input connected to the same input of the control unit; the output of the calculation resolution of the whole part of the control unit is connected to the third input of the first element AND of the device; the output of the resolution of calculation of the fractional part of the control unit is connected to the first input of the second element AND of the device, the second input of which is connected to the output of the clock generator, output the second element And the device is connected to the information input of a frequency divider with a variable division factor and to the input of a frequency divider to five, the output of which is connected to the first input of the third element OR device, the second and third inputs of which are connected to the outputs of the first and third elements AND of the device, respectively, the output of the third element OR of the device is connected to the information input of the third integrator, the sign bit output of which is connected to the input of the sign of transition through O of the control unit, The first and second outputs of the mode control of which are connected to the inputs of the selection of the operation of summation and subtraction of the third integrator and the summation unit ti. respectively, and the characteristic stroke is equal to the second comparison circuit connected to the reset input of the third integrator, the output of the attribute is equal to the first comparison circuit connected to the clock input of the control unit, the output of the mode change resolution of the control unit is connected to the first input of the third And device, the second input of which is connected to the output of the first integrator, the input of the division factor and the strobing input of the divider with a variable division factor are connected to the output of the first integrator and the output sign equally the second comparison circuit, respectively, which is connected Element I is connected to the input of the second trigger, inputs of start and the end of calculations of the control unit are connected to the reset and third input inputs of the third trigger, respectively, the direct output of the third trigger is connected to the first inputs of the second and third elements, second input of the second element This AND, the reset input of the second trigger and the installation input of the fourth trigger are connected to the input of the sign of the calculation window of the control unit, the clock input of which is connected to the second input of the third element AND, the output of the third el AND is connected to the first inputs of the second and third OR elements and the second input of the first element AND, the output of the second element AND is connected to the second input of the second, OR element and the input of the first pulse generator, the output of the first pulse shaper control, the sign of the passage through O which is connected to the reset inputs of the fourth and fifth triggers, the output of the first pulse generator is connected to the inlet of the counter by the input of the sign of the end of the calculation of the control unit, In the control unit, the start input of the block is connected to the first input of the first element OR, the output of the first element OR is connected to the reset input of the first trigger, the inverse output of the first trigger and the forward output of the second trigger are the outputs of the fourth trigger and laziness the integer part and the resolution of the computed inverse output of the fifth trigger of the fraction of the fractional part of the control unit, respectively, the input of the installation of the first pulse generator, the output of which is connected to the second inputs of the first and third e elements OR, the output of the third element OR is connected to the input of the installation of the fifth trigger. dinenets, respectively, with the first and second outputs of the control mode of the control unit, and the output of the divider with a variable division factor is connected to the second informational input of the summation and subtraction unit. the first trigger is connected to the output of the second OR element, the direct output of the first trigger is connected to the first input of the first AND element, the output of the first 0 five 0 five Element I is connected to the installation input of the second trigger, the start inputs and the sign of the end of the calculations of the control unit are connected to the reset and installation inputs of the third trigger, respectively; the direct output of the third trigger is connected to the first inputs of the second and third elements, the second input of the second element, and input reset the second trigger and the installation of the installation of the fourth trigger is connected to the input of the sign of the end of the calculations of the control unit, the clock input of which is connected to the second input of the third element And the output of the third The AND input is connected to the first inputs of the second and third OR elements and the second input of the first AND element, the output of the second AND element is connected to the second input of the second, OR element, and the input of the first pulse shaper, the output of the first pulse shaper , the input of the sign of transition through O which is connected to the reset inputs of the fourth and fifth triggers, the output of the first pulse shaper is connected to the input of the second direct output of the fourth trigger and the inverse output n about soe- trigger pulse generator, the output of which is connected to the second inputs of the first and third elements OR, the output of the third element OR is connected to the installation input of the fifth trigger. the direct output of the fourth trigger and the inverse output of the n one trigger dinenets, respectively, with the first and second outputs of the control mode of the control unit, and the output of the divider with a variable division factor is connected to the second informational input of the summation and subtraction unit. ISSTH5 S + 58 1 IK ty17 f would fob skenisra g Jl CiuMia tttimScpafHeuM Compiled by S.Kulikov Editor A.Ogar Tehred I.Popovich Proofreader T.Kolb Order 1149/47 Circulation: 673; VNIIPI USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 9 "t.3