SU1278865A1 - Device for entering information from discrete transducers - Google Patents

Abstract

The invention relates to the field of engineering, the crucial task of entering discrete information from multi-bit sensors for transmitting it to a data processing device or to a control computer. The aim of the invention is to expand the scope of use by providing the possibility of detecting a faulty sensor discharge or a tire in a communication channel. Due to the introduction of a second register, two AND elements, the NAND element and a trigger, the second counter operates in such a way that the value of its code, issued as a control code at the output of the device, indicates a faulty sensor or bus discharge on the communication channel. 1 il. (L

Description

N5

sj

00 00 O5 Sd

The invention relates to the field of engineering, the crucial task of introducing discrete information from multi-bit sensors for transmission to a data processing device or to a control computer.

The purpose of the invention is to expand the field of application by making it possible to detect a faulty sensor discharge or a bus in a communication channel.

The drawing shows a diagram of the proposed device ().

The device contains the first 1 and second 2 registers, block 3 sravnenik, first 4 and second 5 counters, first 6, second 7, third 8, quarter 9 and fifth 5 And elements, the first 11 and second 12 elements OR, AND-NOT element 13, the trigger 14, In addition, the drawing shows the information inputs 15 of the device, the clock input 16, the setup input 17, the information outputs 18, the output Fault 19, the control outputs 20.

Register 1 contains N bits and is executed on triggers triggered by a falling edge of a clock signal. Comparison unit 3 provides comparison of two W-bit binary codes. Counter 4 is .N-bit and has inputs for writing parallel M-bit binary code into it. The code change at the output of the counter is made on the falling edge of the counting pulse. Counter 5 has N bits and is also triggered on the falling edge of the counting pulse. Register 2 contains K bits and is executed on D-type triggers triggered on the leading edge of a clock signal.

At the entrance; Bus 15 of the device receives information from a multi-bit sensor in the form of a parallel N-bit binary code, and at the input

16 there are pulses with a frequency f ...

The device works as follows .. After turning on the power to the input

17 devices are given a Start signal and register code 1 is overwritten in counter 4, and counter 5 and trigger 4 are reset to zero. The input code is written to register 1 by clock pulses input to input 16. At block 3, binary W-codes are supplied from register 1 and counter 4, Comparison unit 3 compares codes from register 1 and counter 4. If the code from the register is greater than the code of counter 4, the comparison unit generates a More signal that permits the passage of clock pulses through AND 6 to the forward counting counting input ik 4, and if the code from register 1 is less than the counter code, then the comparison circuit produces a less signal that permits the passage of clock pulses through the AND 7 element to the reversible counting input of counter 4, thus, counter 4 tracks the register code 1, which is rewritten into the register 2 by the signal from the element 10, the output code of the register 2 is fed to the information outputs 18 of the device.

If there are random or systematic failures, expressed as loss or over-discharge in the transmitted code, a jump occurs in the value of the transmitted code. In this case, a series of m pulses may be sent to the forward or reverse counting input of counter 4 Depending on the number of pulses in a series, two modes of operation are distinguished.

Mode 1, The number of pulses in a series,

Il1-1 pulses from the output of elements And 6 and 7 are combined by the element OR 11 and fed to the counting input of counter 5, changing its state from zero to m, while the output of the M-th bit of counter 5 stores the logical zero signal, and trigger 14 is zero state. At the end of a series of m pulses, counter code 4 is compared with the register code and the signal Equal to the output of comparison block 3 Equals the clock pulses through the AND 8, OR 12 elements to the reset input of the counter 5 to the zero state.

The operation of elements 6, 7, 9, and 10 is permitted, and the device is provided to monitor the output code after the input code. In case of random obstructions caused, for example, by interference, the comparison unit 3 produces the More or Less signal by no more than. In the m operation cycles of the device, and then the Equals signal appears, ensuring the reset of the counter 5 to the zero state. In this case, the counter 4 can receive no more than m pulses of 3 via the forward or reverse counting input, which is equivalent to the error of the output code of the device no more than –t. units of the least significant bit, and a Failure signal is not generated. Mode 2. The number of pulses in a series of t. A series of pulses arrives at counters 4 and 5. With the arrival of 2 pulses at the output of the Mth bit of counter 5, a single signal appears, setting trigger 14 in a single state. At the output 19 of the device, a Failure signal is set, and a zero signal from the inverse trigger output prohibits the operation of AND elements 8-10. In this case, registers 1 and 2 fix codes generated in them at the time of the failure, and the reset of counter 5 to the zero state is prohibited. After a fault, the codes of counters 4 and 5 continue to change and there comes a time when the codes of counter 4 and register 1 are compared, and the signal that appears at the output of the 3 block of the signal Equals through the IS-HE element 13, allowed by the second input by the Fail , prohibits the operation of elements 6 and 7. Changing the codes in the counters 4 and 5 is stopped, while in the counter 5 a code is generated equal to the number of pulses in the series. The code of the counter 5, issued as a control code at the output of the device 20, indicates a non-corrupted bit sensor or Tina in the communication channel. The number of the faulty bit of the sensor or of the channel is determined by the formula M 1ort, where the nearest integer is indicated in square brackets. For example, t 36, then, i.e. It is likely that the 5th sensor bit is defective. The output of the device to the tracking mode is carried out by applying a signal to the input 17 of the device. Thus, the input information is monitored in the device, and in the presence of a fault, the sensor or bus tire is detected in the communication channel, which simplifies troubleshooting, especially in cases when they are unstable. The device for inputting information from discrete sensors, containing 54 first register, comparison unit, first and second counters, three elements And, the first and second elements IfflU, information inputs of the first register are information inputs of the device, information outputs of the first register are connected to information the inputs of the first comparison unit and the inputs of the preset of the first counter, the first inputs of the elements AND are the clock input of the device, the output of the first element I is connected to the forward counting input of the first with and the first input of the first Element OR, the output of the second element AND is connected to the reversible counting input of the first counter and the second input of the first OR element, the output of which is connected to the counting input of the second counter, the synchronous input of the first counter and the second input of the second element OR are the installation input of the device , the first, second and third outputs of the comparison unit are connected to the second inputs of the And elements, respectively, the outputs of the first counter are connected to the information inputs of the second group of the comparison unit, the output of the third element AND is connected to the first input of the second OR element, the output of which is connected to the reset input of the second counts. that, in order to expand the area when changing due to the possibility of detecting a faulty sensor bit or a tin in the communication channel, a second register, the fourth and fifth elements AND, the NAND element and the trigger, the first inputs of the fourth and n In addition, the elements of And are connected to the clock input of the device, the outputs of the first counter are connected to the information inputs of the second register whose outputs are the information outputs of the device, the outputs of the second counter are the control outputs of the device one of the counter; connected to the S-input of the trigger; R-input (Some connected with the synchronous input of the first counter and the second input of the second element OR; the forward output of the rigger is connected to the second input of the element IS-NOT and is the output of the device malfunction, and the inverse is connected with the third input of the third, the second inputs of the fourth and that elements And, respectively.

the output of the fourth element I is connected to the synchronous input of the first register, the output of the fifth element I is connected to the synchronous input of the second register, and

the third inputs of the first and second elements AND are connected to the output of the NAND element, the first input of which is connected to the third output of the comparison unit.

Claims (1)

Claim A device for inputting information from discrete sensors, comprising a first register, a comparison unit, a first and a second s.schetchniki, three elements And, the first and second elements of the UTI, the information inputs of the first register are the information inputs of the device, the information outputs of the first register are connected to the information inputs of the first groups of the comparison unit and the preset inputs of the first counter, the first inputs of the AND elements are the clock input of the device, the output of the first AND element is connected to the direct counting input of the first counter and the first input of the first OR element, the output of the second AND element is connected to the reverse counting input of the first counter and the second input of the first OR element, the output of which is connected to the counting input of the second counter, the clock input of the first counter and the second input of the second OR element are the installation input of the device, the first , the second and third outputs of the comparison unit are connected to the second inputs of the elements And, accordingly, the outputs of the first counter are connected to the information inputs of the second group of the comparison unit, the output of the third element connected to the first input of the second OR element, the output of which is connected to the reset input of the second counter, characterized in that, in order to expand the scope by providing the possibility of detecting a faulty discharge of the sensor or bus in the communication channel, a second register, fourth and fifth AND elements, AND element AND trigger, the first inputs of the fourth and fifth elements AND are connected to the clock input of the device, the outputs of the first counter are connected to the information inputs of the second register, the outputs of which are info device outputs, the outputs of the second counter are the control outputs of the device, one of the outputs of the second counter is connected to the S-input of the trigger, the E-input of which is combined with the clock input of the first counter and the second input of the second OR element, the direct output of the trigger is connected to the second input of the And NOT is the output Device failure, and the inverse output is connected to the third input of the third, second inputs of the fourth and fifth elements AND, accordingly, the output of the fourth element AND is connected to the clock input of the first register RA, the output of the fifth AND element is connected to the sync input of the second register, and the third inputs of the first and second AND elements are connected to the output of the NAND element, the first input of which is connected to the third output of the comparison unit.