SU1277141A1 - Dividing device - Google Patents

Abstract

The invention relates to the field of automation and computing. The device comprises a pulse period-to-code converter, a pulse generator, first and second counters, an AND element, a synchronization node, and an output register. The period converter is made on the reference frequency generator, the synchronization node, the period counter and the period register. In the course of operation, the code for the current period value of the first pulse sequence is generated at the output of the period converter. This code is the preset code of the first counter, which forms at its zero output a sequence of pulses that fill the second counter before the time of the end of the current period of the second pulse sequence. At this point in time, the ratio of the periods of the pulse sequences is read into the output register of the code. Accuracy increase is achieved with due to the separation of the preset code in the first counter (L with respect to updating the information in the period register of the period converter. 1 Cp f-ly, 3 Il.

Description

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vl 11 The invention relates to automation and computing and can be applied in computing devices with a frequency-pulse form of representation of information. The aim of the invention is to improve the accuracy of calculations for, by eliminating failing situations. Figo 1 is a block diagram of a dividing device; in Fig 2, a diagram of a synchronization node is shown; in fig. 3 B1 emein device operation diagram. The split device (Fig. 1) contains a converter 1 of a pulse following period into a code, a generator of 2 pulses, the first and second counters 3 and 4, the output register 5, the synchronization node 6, element 7, the converter 1 is made on the Xcneur 8 reference frequency j node 9 synchronization, the counter 10 period register 11 period. The device thus includes the output 12 of the generator 8, the forward and inverse outputs 13 and 14 of the synchronization unit 9, the output 15 of the generator 2, the output 16 (direct) of the node. 6 synchronization Each synchronization node contains (fig. 2) differentiating day 17f RS - TpHrrep 1 8 and zomelg. I. 19, The device performs e; t calculating the code for the ratio of the periods T1 T2 of the following h. Pulses and working. At the inputs of the Bx. 1 and Bx, I are fed (T1, j, Tip, ,,,, J T2 ,;. T2,,,.,, Engraved, for example, by the leading fronts of signaling pulses (Fig. 3) o Generators 2 and 8 produce impulses with squared-gast1, approximately equal to 2, and with a frequency; the determined allowable error of quantization of the intervals T1 and 12, the ratio between 1, and the frequencies f and f, of the helixes 2 and 8 are determined by the allowable the methodological component is 1-1-s. calculating the T2 / T ratio as well as the chosen unit of reference for this ratio. The possibility of independent adjustment of f and r ,,, is due to The oscillator color j sets the required, a, w-th. pairs of calculation msg. Counters 3, Ai 10 are chosen so that their content is measured at the counting input (+1 or occurs by a positive transition of the input pulse, set to 1 o - also by the positive differential signal at the input R (moments t-, t., fig. 3) J and the preset is writing the number from register 11 to counter 3 - by the negative differential signal at input C, to such a level. VIS are satisfied, for example, by counters made on the basis of 155IE7 chips. Writing to registers 5 and 11 of the parallel code is made at the time of a negative signal drop at input C2 (moments t ,,, t, fig. 3). Items 7, 19 operate at low levels, i.e. a low level signal appears at their outputs only when low levels are present at both inputs. The synchronization node 6 (9) (Fig. 2) operates in such a way that when a negative differential appears at its input 20 at its direct output 16 (13), a short low level pulse appears, and at the inverse output 14 there is the same high impuls level, which in terms of phase multiplication correspond to a low level of the pulse signal at the inputs. Thus, the moments of recording in the counters at inputs -I, into registers 5 and 11 at inputs C2, set to O at inputs 11, and preliminary recording with control at input C are always separated in time. In the course of operation, after the 2nd pulse T1, according to a negative differential signal 13 at time t; (Fig. 3) from counter 10, register 11 records the contents of counter 10. In this example, the code corresponds to the interval T1i, the contents of register 11 are updated after each interval 11 (T1, T1,. With the arrival of the first pulse, the output signal 16 (positive difference at time t,) counters 3 and 4 are set to O by inputs R. On the input 0 of counter 3, a negative difference appears, corresponding to the phase position of the low level of signal T1 (if output 14 is low), at input C of counter 3 there is a negative differential, and it contains e register 11 is rewritten into the counter 3. The counter unit 4 is recorded first. Then, as the arrival of countable pulses to the subtracting input -1

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the contents of counter 3 are reduced, and when the zero state is reached, the second unit is recorded in counter 4, and the contents of register 11 are recorded in counter 3 again. The process continues until the second pulse T2 appears, and output 6 is generated at output 16. . The negative differential of this pulse in register 5 at time t5 (Fig. 3) records the contents of counter 4. On the output buses of register 5, an N code is formed, which is the result of dividing T2 / T1 cG with an accuracy to the remainder. At the output, the appearance of a pulse means a change of the output code. In addition, the low level at the output signals that at this time there is a change of information in register 5 and the output code may be unreliable.

Then, by a positive differential at time t (Fig. 3), counters 3 and 4 are installed in O. The process continues,.

Thus, in the proposed device, an increase in the accuracy of operation is achieved due to the separation in time of the formation of a period code at the output of converter 1 (register 11) and its census into counter 3.

Claims (2)

Formula invented and. 1, A separating device containing a pulse-to-code period converter is connected to the first information input of the device and the output to the setup input of the first counter connected by a counting input to the output of the pulse generator and the clock input of the synchronization node connected by a signal input to the second information input device as well. output - to the reset inputs of the first and second counters and the control input 14 recording the output register, the information input of which is connected to the output of the second counter, connected by a counting input to the output of zeroing the first counter, characterized in that, in order to improve the accuracy of the calculations by eliminating faulty situations, an And further period converter is introduced into it Pulses in the code contains a reference frequency generator, a period counter, a period register and a synchronization node connected by a clock input to the output of the reference frequency generator and a counting counting input period a, with a signal input with an input of a pulse period to code converter, a direct output with a reset input of a period counter and a record control input for a period register, and an inverted output with a first input of an And element connected with a second input to the zero output of the first counter, and the output is connected to the control input of setting the code of the first counter, while the output of the period counter is connected to the information input of the period register, the output of which is the output of the pulse-period-to-code period converter. 2. The device according to claim 1, that is, so that each synchronization node contains a differentiating circuit, an RS flip-flop and an I element connected by the first input to the clock input of the synchronization node, the second input to the forward output of the RS flip-flop, and the output to the forward output of the synchronization node and the S-input of the RS flip-flop connected by an inverse output with the inverse output of the synchronization node, and the R-input to the output of a differentiating circuit, whose input is connected to the evil sync 3 input signal, tpue.i 12 Tt cfJue.Z