SU1273994A1 - Device for checking errors in magnetic recording-reproducing of digital information - Google Patents

Abstract

The invention relates to digital magnetic recording and allows for improved control accuracy. Errors in the reproduced test signal are coupled in the device by element-by-element comparison on the adder 3 of a reproducible pseudo-random sequence of symbols with a reference sequence. In the absence of synchronism, a pseudo-random error sequence is generated at the output of the adder 3, to which the detector 10 responds, the output of which produces a signal that switches the trigger 9. The shift register 16 and the adders 17 and 18 form the detector 10, which operates on the principle of checking the pseudo-random signal sequence for compliance with its code-coding rule. The output signal of the trigger 9 is fed to the control input of the switch, which connects the information input of the shift register 5 to the input bus 1 of the playback signal of a pseudo-random sequence. The gating element 11 converts the signal of a flare into a sequence of pulses of opshbok counted by the counter 12. 1 Il. I CH1 OP with

Description

The invention relates to instrumentation, in particular, to a technique of digital magnetic recording, and can be used in means of controlling magnetic recording equipment for measuring the number of transmission errors of digital data by magnetic recording-reproduction channels.

The aim of the invention is to improve the accuracy of the control.

The drawing shows a functional diagram of the device.

The device contains a pseudo-random sequence (characters) playback signal input bus 1, a playback clock signal input bus 2, first and second adders 3 and 4 modulo two, first and second shift registers 5 and 6, switch 7, error detector 8, trigger 9 , a pseudo-random error sequence detector 10, a gating element 11, and a 12 error counter.

The detector 8 includes an inverter 13, a D-trigger 14 and a counter 15.

The detector 10 contains a shift register 16, the first and second adders 17 and 18 modulo two, the first and second inverters 19 and 20, the multi-input element OR 21, the AND-HE22 element, the D-flip-flop 23 and the counter 24.

The input bus 1 is connected to the first signal input of the switch 7 and to the first input of the adder 3, the output of which is connected to the first information input M of the detector 8, to the first information input of the detector 10 and to the information input of the shift register b. The output of the switch 7 is connected to the information input of the shift register 5, the outputs of two bits of which are connected to the first and second inputs of the adder 4, the output of which is connected to the second signal input of the switch 7 and the second input of the adder 3. The detector 10 is connected to the first input of the trigger 9, the second the input of which is connected to the output of the detector 8. The output of the trigger 9 is connected to the control input of the switch 7 and to the setup input of the register 6, the output of which is connected to the first signal input of the gating element I1, the output of which En with the input of the counter 12 errors. The input bus 2 is connected to the clock input of the register 5 shift, with the second clock

the input of the detector 8, with the second clock input of the detector 10, with the clock input of the shift register 6 and with the second strapping input of the gating element 1 1.

The first input of the detector 8 is connected to the D-input of the D-flip-flop 14, the direct output of which is connected to the installation input of the counter 15, the output of which

connected to the output of the detector 8. The second input of the detector 8 is connected to the counting input of the counter 15 and to the input of the inverter 13, the output of which is connected to the C-input of the D-flip-flop 14.

5 The first input of the detector 10 is connected to the first input of the adder 17 and to the information input of the shift register 16, the outputs of all bits of which are connected to the inputs of the multi-input

0 of the OR element 21, the output of which is connected to the first input of the NAND element 22. The outputs of the two bits of the shift register 16 are connected to the first and second inputs of the adder 18, the output of which is connected to the second input of the adder 17, the output of which is connected to the input of the inverter 19, The output of the inverter 19 is connected to the second input element AND-NOT 22, the output of which is connected to the D-input of the D-flip-flop 23, the output of which is connected to the installation input of the counter 24. The second input of the detector 10 is connected to the counting input of the counter 24, to the clock input of the register

5 shift 16 and to the input of the inverter 20, the output of which is connected to the C-input of the D-flip-flop 23. The output of the counter 24 is connected to the output of the detector 10.

The specific performance of individual elements and components is as follows.

The 5th and 16th shift registers are seven bits. The inputs of the modulators two 4 and 18 are connected to the outputs of the sixth and seventh bits of shift registers 5 and 16. Switch 7 connects the information input of shift register 6 to the input bus 1 if there is a trigger 9 output signal at the control input of the switch. the trigger signal 9, the switch 7 connects the information input of the register 5 to the output of the adder 4.

Claims (1)

5 The counter-counter module 15 and 24 is equal to 16, i.e., the signal at the output of these counters is received after 16 clock ticks of the playback clock when there is no signal at this time at the set inputs of the counters. The number of bits of the shift register 6 is 24. The second input of the gating element 11 is inverse, i.e. gating the output signal of shift register 6 is performed by the second negative half-wave clock sync playback signal. The device works as follows. The register 5 and the adder 4 form the case when the information input of the shift core 5 is connected via the BOM of the switch 7 to the output of the adder 4, a generator of the reference pseudo-random character sequence, identical to the generator (not shown), which forms a test pseudo-random number that is written to a magnetic carrier (not shown) sequence of characters. Errors in the reproduced test signal are extracted in the proposed device by element-by-element comparison on the adder 3 of the reproducible pseudo-random sequence of symbols with the reference sequence. With a reference pseudo-random sequence, the sequence must be formed element-wise synchronously with the reproducible sequence. In synchronism with the reproducible pseudo-random sequence, the generator of the reference pseudo-random sequence is introduced by connecting via the switch 7 the information input of the register 5 to the Input bus 1. In the absence of synchronism between the reference pseudo-random sequence at the output of the adder 3, a pseudo-random sequence of errors is formed. Detector 10 responds to this successively, at the output of which a signal is generated that switches the trigger 9. The detector 10 operates as follows. The pseudo-random error sequence goes to the information input of the shift register 16 and to the first input of the adder 17. The second input of this adder receives a signal from the output of the adder 18 connected to the outputs of the two bits of the shift register 16, corresponding to the two bits of the shift register 5, to the outputs of which connected adder 4.. As a result, the shift register 16 and adders 17 and 18 form a known error detector, which operates according to the principle of checking the input signal (in this case, the output signal of the error of the adder 3) of a pseudo-random sequence for its code-coding rule. As a result, when an error-free pseudo-random error sequence arrives at the first input of the detector 10, a constant low level of logical C is formed at the output of I7, and a high level of logical 1 is output at the output of the inverter 19. At the same time, a high level of constant This is also formed at the output of the multi-input element AND 21, since at least one of the bits of the register 16 will necessarily have a logical 1. At the same time, the output of the AND-NOT element 22 is low th read clock timing difference reproduction is recorded in the D-flip-flop 23. As a result we at the output of this flip-flop continuously formed low level, whereby the mounting of the lock is removed entry counter 24, which starts podschitshat serial clock. After 16 (for this example) clocks at the output of the counter 24 and, therefore, at the output of the detector 10, a signal is generated. The presence of a D-flip-flop 23 is associated with the need to exclude 24 false short duration pulses arriving at the installation input of the counter, generated by the output of the adder 17 at the beginning of the clock positions due to non-simultaneous arrival of signals at its outputs. The OR element 21 prevents the output signal from being formed by the detector 10 in the case of a sequence of zeros arriving at its first input. The output signal of the trigger 9 is fed to the control input of the switch 7, which at the same time connects the information input of the shift register 5 to the input bus 1 of the playback signal of a pseudo-random sequence. Seven (for this example of register bit 5) clocks, i.e., after filling the shift register 5 with a reproducible pseudo-random sequence, the error signal at the output of the adder 3 ceases to form, to which no error detector 8 responds. After sixteen (for this example of the counter 15 counting module), a signal is generated at the output of the detector 8, which resets the trigger 9 to the initial state. The D-flip-flop 14 in the detector 8 protects the counter 15 from arriving at its installation input of spurious short duration pulses generated at the output of the adder 3 at the beginning of clock positions due to non-simultaneous arrival of signals at its inputs. Therefore, the output signal of the adder 3 in D-flip-flop 14 is produced in the middle of a clock pulse. After the trigger 9 is switched to the initial state, the signal from the control input of the switch 7 is removed, which at the same time connects the information input of the shift register 5 to the output of the adder 4. Next, the register 5 and the adder 4 begin to generate a reference pseudo-random sequence of characters, but it is synchronous with reproducible sequence. An error at the output of the adder 3 is generated in case of a mismatch of the next character of the reproduced pseudo-random sequence with the corresponding symbol of the reference sequence. The error signal is generated in the potential BVN code (without returning to zero) and is fed through register 6 to the first input of gating element 11. Element 11 performs the conversion of the error signal in the BVN code (errors in this code correspond to a high level of logical 1) into a sequence of error pulses which is counted by 12 errors. The length of an error bundle that is unmistakably allocated by a device is not limited. After a possible playback clock sync signal in the magnetic recording channel, the synchronism between the reference and reproducible pseudo-random sequence is disturbed. When this automatic input device in synchronism with the reproducible sequence using the detector 10, the trigger 9, the switch 7 and the detector 8 is similar. During the acquisition of a pseudo-random sequence of errors by the detector 10, which lasts for this example of the 23 clock cycle, a certain amount of errors generated at the output of the adder 3 is a result of a synchronization disorder, but is not a reproduced signal error. To eliminate the arrival of this number of false errors, the buffer register 6 is assigned to the input of counter 12, and its corresponding bit size is 24. After switching the trigger 9, its output signal goes to the setup input of shift register 6 and zeroes all its bits in which the required number of false errors was recorded at this time. False errors generated at the output of the adder 3 during the input of the device in synchronism, which includes filling the register 5 and capturing the output zero signal of the adder 3 with the detector 8, also do not arrive at the input of the error counter t2, because at this time the shift register 6 will be locked in the zero state by the output signal of the trigger 9. Formula of the invention. Device for error control. magnetic recording-reproducing digital information containing the first adder modulo two, one input connected to the input bus of the pseudo-random sequence playback signal, the first shift register, outputs connected through the second modulo two and the first modulo-two adder to the first error-free detector input and a second shift register connected in series, a gate element and an error counter, with the clock inputs of the shift registers and the second inputs of the detector without errors and this gates are connected to 71 input clock clock sync playback, characterized in that, in order to improve the control accuracy, a switch, a pseudo-random error sequence and a trigger detector are inputted to it, the output of the first modulo two and the input clock of the clock synchronization signal are connected respectively to the first and second inputs pseudo-random error sequence detector, the output of which is connected to the first trigger input, the output of the error-free detector is connected to the second 73994I the trigger input, the output of which is connected to the control, input of the switch and with the installation input of the second shift register, the input bus of the playback signal of the pseudo-random sequence and the output of the second modulo two are connected respectively to the first and second signal M inputs of the switch, the output 10 which is connected to the information input of the first shift register, the output of the first north-west telecom module modulo two is connected to the information input of the second register 15 shift.