SU1257709A1 - Storage with error detection and correction - Google Patents

Abstract

The invention relates to computing, in particular, to storage devices. The aim of the invention is to increase the reliability of the control and simplify the device. The device contains an address register, a counter, a control unit, shift information registers, a first control shift register, a first parity signal generator, a comparison unit, two decoders, a correction unit, a drive consisting of the information and main control parts, into which an additional control part is inserted. , as well as the newly introduced selector, the second control shift register, the second driver of the parity signals and the multiplexer. The second parity signal generator generates pilot signals that are recorded in the information word bits along the diagonal, which allows detecting triple errors in the accumulator and thereby increasing the reliability of the control. At the same time, the number of check bits - flOB in a word does not depend on the word depth and is always equal to two, thereby simplifying the control part of the strings and reducing the number of control shift registers, which simplifies the device. 2 Il. 1 tab. with S (L o so

Description

to

The invention relates to: computer hardware, in particular to recording devices.

The aim of the invention is to increase the reliability of the control and simplify the device.

On presents a functional diagram of the proposed device; FIG. 2 is a functional diagram of an embodiment of an α-control unit;

The device contains (figure 1) the selector 15 clock input 2 device-. on. The device also contains a register of 3 addresses, a counter 4, a control block 5, a block 6 containing information | shift shift registers 7, first 8 and second 9 control shift registers, accumulator 10, consisting of information 1, main 12 and additional 20 13 control parts, first 14 and second 15 parity signal generators, comparison block 16, first 17 and the second 18 decoders, the multiplexer 19 and the block 20 of the correction. FIG. control 21 and 22 and address 23 inputs of the device, first address input 24 of accumulator 10, information 25 and control 26 inputs of the device, outputs 3D and 27 and 28 of the selector 1, installation inputs 29 and outputs 30-32 are marked . ditch 7-9, input 33 and second setup input 34 of register 9., input 35 of counter 4, first control input 35 36, second and remote input 37, information 38, control 39 and 40, second control input 41, information 42 and control 43 and 44 outputs of accumulator 10, inputs 45 and 46 40 of comparison unit 16, control input 47 of multiplexer 19, outputs 48 and 49 of decoder 17, outputs 50-52 of comparison unit 16, inputs 53-57 and outputs 58 of multiplexer 19 , informational 59 and control 60 outputs of the device.

The control unit 5 contains (FIG. 2) triggers 61-64, counters 65 and 66, elements AND 67-74, element OR-NOT 75, 50 element OR 76, elements 77-79 of delay, and trigger 80.

In the device, the number of test bits per word does not depend on the word size, but is always equal to two. 55 In addition, the device has a minimum number of words in the information block that are processed at one time.

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equal to the number of information bits of the word.

The device works as follows.

According to signals received at input 22 in register 3 from input 23, the nomen address of the information block is entered and block 5 is initiated. The address code from register 3 to input 24 enters accumulator 10. Input information with test bits from inputs 25 and 26 through

the selector 1, by a signal from input 21, is set at inputs 27 and 28 of registers 7 and 8. According to the signals from block 5 via inputs 29, the recorded information is entered for intermediate storage in registers 7 and 8 by the word. And for each signal from input 29 (RT) enters a new word in registers 7 and 8 and shifts the -I-1 of the previous word. Synchronously with the advancement of information 1 and the registers 7 and 8, the driver 14 of the information received at the input 30, generates the control signals (K) for each word. At the same time, continuous monitoring of the correctness of information advancement in registers 7 and 8 is carried out by comparing the control signals in register 8 with the control signals obtained in the driver 14. The comparison is performed in block 16 and the result is output 50.

At the end of the filling of registers 7 and 8, the driver 15, from the information entered in the registers 7 and 8 and fbiromer 15 through the information inputs 30 and 31, generates diagonal tell-tales (D). Signals D in register 9 are recorded at inputs 33 by a signal at input 34 at the moment when the control signals D are formed at outputs 33. Then block 5 generates signals arriving at input 35 to counter 4 and input 36 to accumulator 10. By this signal the counter 4 enumerates the addresses of the accumulator 10. Synchronously with this, the signals on the inputs 29 with a delay equal to the recording time in the accumulator 10 shift the information from the registers 7-9 to the accumulator 10 on the inputs 38-40. At the same time, from block 5, recording pulses are inputted at input 41 to accumulator 10. Thus, the entire block of information with control signals K and D is squeaked into accumulator 10.

the selector 1, by a signal from input 21, is set at inputs 27 and 28 of registers 7 and 8. According to the signals from block 5 via inputs 29, the recorded information is entered for intermediate storage in registers 7 and 8 by the word. And for each signal from input 29 (RT) enters a new word in registers 7 and 8 and shifts the -I-1 of the previous word. Synchronously with the advancement of information 1 and the registers 7 and 8, the driver 14 of the information received at the input 30, generates the control signals (K) for each word. At the same time, continuous monitoring of the correctness of information advancement in registers 7 and 8 is carried out by comparing the control signals in register 8 with the control signals obtained in the driver 14. The comparison is made in block 16 and the result is output 50.

At the end of the filling of registers 7 and 8, the driver 15, from the information entered in the registers 7 and 8 and fbiromer 15 through the information inputs 30 and 31, generates diagonal tell-tales (D). Signals D in register 9 are recorded at inputs 33 by a signal at input 34 at the moment when the control signals D are formed at outputs 33. Then block 5 generates signals arriving at input 35 to counter 4 and input 36 to accumulator 10. By this signal the counter 4 enumerates the addresses of the accumulator 10. Synchronously with this, the signals on the inputs 29 with a delay equal to the recording time in the accumulator 10 shift the information from the registers 7-9 to the accumulator 10 on the inputs 38-40. In this case, from block 5, recording pulses are inputted at input 41 to accumulator 10. Thus, the entire block of information with control signals K and D is sounded in accumulator 10.

Reading mode

Flo to signals arriving at input 22 of L register 3 is entered into the address of the information block at input 23, which is transmitted at input 24 to accumulator 10 and block 5 is started. Block 5 outputs signals at input 36 of accumulator 10. According to signals received at inputs 21 and 22, block 5 generates a signal at output 35, which starts counter 4. Information with check bits (D) and (K) is read from accumulator 10 and by signals: at inputs 29 through selector 1 it is entered into registers 7-9 by outputs 42, 43, 27, 28 and 44.

Then, the control signals (K) and (D) of the formatter f и 14 and 15 are formed. The control signals generated by the former 15 are not recorded in register 9 (as during recording), but are transmitted simultaneously with the signals from the former 14 through inputs 33 and 45, respectively in block 16. According to the signal coming from block 5 on exit 46, the results of comparing the contents of registers 8 and 9, the formers 14 and 15 in block 16 are fixed. When comparing the control signals (K), signs C are formed, Dov (D) - signs of M, priv dennye table. As can be seen from the table, for the values of the signs M and C given in section 8, lines eight - ten, the correction of the triple error is possible. The type of error in the table is the result of an analysis of possible errors that occur during operation of the device. The analysis took into account the presence of triple errors, since a larger number of errors are unlikely.

The counter 66 of block 5 outputs a series of pulses to output 48, which control the operation of multiplexer 19. The problem of recognizing the type of error by the signs is performed by the decoder 17. If the error is corrected, a signal is output from the decoder 17 on output 49 which enables the operation of multiplexer 19 for error correction. If there is an error, but it is not corrected, then a corresponding true signal is output on output 48, and on output 49 - a signal to prohibit the operation of multiplexer 19, excluding the 1st case of false correction. Descrambler 18

25

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identifies the bits of drive 10 that failed.

Correction of distorted information is as follows. The initial state is at the output of registers 7–9, the first word, which is supplied via outputs 38 and 39 to block 20. If the control signals in block 16 did not occur, i.e. It turned out that there was a discrepancy between the contents of the control bits read directly from accumulator 10 and formed from informational words., Then at outputs 51 and 52, signs M and C are different from logical O (if there is no error, they are equal to logical O). These signs are decrypted in the decoder 18 and as a result at one of its outputs 0 53 and 57 a logical 1 signal is turned on, indicating the location of the faulty bit in the drive 10. The decoder 17 recognizes the type of error (in accordance with the table), and if it is corrected outputs a permission signal at output 49 on the m Liplexer 19. Counter 66 (Fig. 2) of block 5 is in the zero state (for example, for five words 0, the counter is in the 0: 0: 0 state). The parallel code of the counter 66 at the output 48 is supplied to the multiplexer 19, which connects the result of the decryption of signs for the first word 5 to the input of the block 20. When an oyibka occurs in the first word, one of the outputs 58 shows a logical O and the corresponding output of the outputs 59 or 60 according to the information, the inverse of the incoming through the inputs 38 or 39, i.e. Correction of the error occurred while reading the information. Then meter 66 will change its state to (0: 0: 1) and simultaneously 5 with this, the signal at input 29 will advance information in registers 7-9. As a result, at outputs 38 and 39, the second word will appear. Multiplexer 19 connects the result of deciphering prints for the second word to the input of block 20, thus the correction process is repeated for all c-lines. If there are no errors, then the output of the decoder 18 is zeros and, accordingly, rr is set to 5, and the output of multiplexer 19 is the units that I authorize to pass information through the block .. O without change.

p yes (D)

1C

IM

Incomparability of bits (D) and (k)

C

2M

2M

3M

Incomparability of two bits (D)

Incomparability of two bits (D) and 2 bits (K)

Comparison of three bits (D)

2C

3M

Incomparability of two Triple O & & - Discharge (K) and ka three discharge (D) are not corrected

IM

3M

Incomparison between two bits (K) and one bit (D)

Incomparability of three bits (K) and three bits (D)

IM

Incomparability of three bits (K) and one bit (D)

1C

3M

Incomparability of the three bits (D) and one bit (K)

1C

2M

Incomparability of the 1st bit (K) and 2 bits (D)

p d (D)

Corrected in4 bit or (k) times p d

Not corrected

Not corrected

Not corrected

Triple error- Not corrected

ka

Three information bits or (K) bits are corrected.

 Three information bits or two information bits and one (K) bit are corrected.

Three information bits or two information bits and one (K) bit are corrected.

Double error - not corrected

Claims (1)

Invention Formula A memory device with error detection and correction, containing an address register, a counter, information shift registers, a first control shift register, a first parity signal generator, a comparison unit, decoders, a control unit, a correction unit, and a drive consisting of the information and main control parts, the first input of the control unit is the first control input of the device, the second control input of which is the second input of the control unit and the control input of the address register, the input The cost and the third input of the control unit are respectively the address and clock inputs of the device, the outputs of the address register and the counter are connected to the address inputs of the accumulator, one of the outputs of the information shift registers is connected to the information inputs of the accumulator and the inputs of the first group of the correction block, whose input and control the input of the main accumulator is connected to one of the outputs of the first control shift register; the first output of the control unit is connected to the installation inputs of information and the first control shift registers, the other outputs of which are connected respectively to the inputs of the first generator of parity signals and to the inputs of the first group of the comparison unit, the inputs of the second group of which are connected to the outputs of the first generator of parity signals, and one of the outputs from the inputs of the first and second decoders, the input and outputs of the counter are connected respectively to the second output and to the even. the control unit input, the third and fourth outputs of which are connected to drive control inputs, information and control 50 20 five 0 five The device's outputs are the outputs of the correction unit, the first output of the first decoder is the first indicator output of the device, which is because, in order to increase the reliability of monitoring and simplifying the device, the second parity generator, the second control shift register, additional control part of the accumulator, selector and . multiplexer, the inputs and outputs of which are connected respectively to the output of the second decoder and to the inputs of the second group of the correction unit, and the control inputs to the second output of the first decoder and to the fifth output of the control unit, respectively, the first and sixth outputs inputs of the second control shift register, one of the outputs and inputs of which are connected respectively to the input and Ki output of the additional control part of the accumulator, other outputs and inputs of the second control shift register connected, respectively, to the inputs of the third group of the comparison unit, to the outputs of the second generator of the parity signals and inputs of the fourth group of the comparison unit; the inputs of the second generator of the parity signals are connected to other outputs of the information and first control shift registers, the inputs of which are connected to the outputs of the selector, one of the inputs which are connected to the information and control outputs of the accumulator, the other inputs of the selector are the information and control inputs of the device, and the control input below for prison to the first input of the control unit, a seventh output coupled to a control input of the comparing unit, another output of which is the second output indicator ustroy-, Properties. i yy 69 Editor Y. Sereda Order 5031/51 Circulation 543 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Rauschska nab., 4/5 Production and Printing Enterprise, Uzhgorod, Projecto st., 4 L. “f x Ez T} fig g US Compiled by T. Zaitseva Tehred I.Popovnch Proofreader I.Musk