SU1256163A1 - Generator of pseudorandom binary sequences - Google Patents

Abstract

The invention relates to a pulse technique. The purpose of the invention is to expand the functionality of the device. The generator comprises a memory block 4, registers 6 and 7, and a control block 9. The introduction of source 1 of pseudo-random codes, switches 2 and 5, register 3, block 8 elements AND, and block 10 elements OR allows to obtain pseudo-random sequences with a controlled probability of occurrence of a single symbol ol. 1 3.p. f-ly, 3 ill. (L ffitrf Stal

Description

The invention relates to a pulse technique.

The purpose of the invention is to enhance the functionality by obtaining pseudo-random sequences with a controllable probability of occurrence of a single character. Fig, 1 shows the functional diagram of the generator of pseudo-random binary sequences; in fig. 2 is a diagram of the control unit J in FIG. 3; timing diagrams of the operation of the control unit.

The pseudorandom binary sequence generator contains the source 1 pseudorandom codes, first switch 2, third register 3, memory block 4, second switch 5, first 6 and second 7 registers, AND block 8, control block 9, OR block 10, bus 11 Start The outputs of the first register 6 are connected to the inputs of the second register 7, the outputs of which are connected to the information inputs of the memory block 4, the first and second control inputs of which are connected to the first and second outputs of the control block 9, the third output of which Fitting of the connections to the input of the first register 6, the Start Bus 11 is connected to the input of the control unit. The outputs of block 10 of the OR elements are connected to the synchronization inputs of the corresponding bits of the second register 7 and first register 6, the information inputs of the bits of which are connected to the corresponding outputs of the second switch 5, the first group of inputs of which are connected to the outputs of memory block 4, the address inputs of which are connected to the outputs of the first switch 2, the first group of inputs of which is connected to the outputs of the third register 3, the inputs of which are connected to the second group of inputs of the first switch 2 and the first group of outputs of the source In the first pseudorandom code, a group of outputs of which are connected to the first inputs of elements AND block 8 of elements AND whose outputs are connected to the first inputs of elements OR of 10 elements OR, the second inputs of elements. OR of which are connected to the fourth output of control block 9, the fifth output connected to the second inputs of the elements And block 8 elements And and

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the input of the second switch 5, the second group of inputs of which is connected to the outputs of the second register 7. The sixth output of the control unit 9 is connected to the control input of the third register 3 and the first input of the source 1 of pseudo-random codes, the second input of which is connected to the third output of the control unit 9, the first output which is connected to the input of the first switch 2,

The control unit 9 (Fig. 2) contains a generator of 12 clock pulses, an initial setup circuit 13, a trigger 5, 14, an AND 15-18 chip. shift register 19, three elements OR 20-22, the first inputs of which are connected to the input of control unit 9 and the first input of trigger 14, the output of which is connected to the first input of the first element 15, the output of which is connected to the first inputs of the second 16, third 17, fourth 18 And elements and with the synchronization input of the shift register 19, the corresponding outputs of which are connected to the second inputs of the second 16, third 17 and fourth 18, respectively. And the output of the second element AND 16 is connected to the second input of the second element OR 21 and the first IL element And 20, the third input of which is connected to the output of the fourth element AND 18 and the second input of the third 5 element OR 22, the output of which is the same output of control unit 9, the third output of which is connected to the second input of the trigger 14, the first output of the initial installation circuit 13 control input and the second information input of the shift register 19, the first information input of which is connected to the output of its last bit and the first output of control unit 9, the second, fourth and fifth outputs of which are respectively the outputs of the first of 20, the second OR element 21 and the third AND gate 17. The output of clock 12 is connected to a second input of the first AND gate 15. A second output of circuit 13 is connected to the initial setup to a third data input of shift register 19.

The source 1 of pseudo-random codes is implemented by the known ones, which ensures the generation of recurrent codes.

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sequences of pseudo-random cds, circuits that implement the characteristic polynomial

.

The memory unit 4 is filled in such a way that it provides at the output of each bit a predetermined probability of occurrence of units. For this, the total number of units in the ith category of all memory cells is g. should be chosen on the basis of the ratio P g / M, where P is the given probability of occurrence of units at the output of the i-th bit, M is the number of memory cells.

The pseudo-random binary sequence generator works as follows.

After the power is supplied, the setting circuit 13 outputs a single pulse, setting trigger 14 and the first register 6 to the zero state, code 001 is written to the shift register 19, and the source 1 of pseudo-random codes is set to the initial non-zero state. The supply of a single signal to the bus 11 Start provides recording from the memory block 4 to the register 6 of the cell contents with the address generated at the outputs of the source 1 pseudo-random codes. This address is recorded in the third register 3, and a new code is generated in the source I of the pseudo-random codes. In addition, a single signal on bus 11 Start triggers trigger 14 into a single state, and control unit 9 begins to generate a sequence of control pulses in accordance with the time diagram shown in FIG. 3

In the first cycle of the operation cycle of the device, the memory 4 is activated by the signal from the second output of control block 9 (FIG. 36) and the code recorded at the address generated on the first group of outputs of source 1 of pseudo-random codes is entered into register 6, and - my register 6 according to the signal from the fourth output (Fig. 3e) of control block 9 is rewritten into register 7. Thus, in register 6 there is a code stored in memory block 4 at the address formed on the first group of pseudo-random code source outputs .

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In the second cycle of operation of the device, the codes in registers 6 and 7 are mixed. To ensure random mixing, the code formed on the second group of outputs of source 1 of pseudo-random codes is fed to the first inputs of block 8 of elements And, to the second inputs of elements And which receives a signal from the fifth output (fig. 3g) of the control block 9. The same signal connects the outputs of register 7 through the second switch 5 to the inputs of register 6. At the same time, if the pseudo-random code in the 1st section has 1, then the corresponding output of the 8-element block And the synchronization pulse received through the 10-element block OR to the synchronous inputs of the corresponding bits of registers 6 and 7. Under the action of these synchronization pulses, the information in the selected bits of registers 6 and 7 changes places. If the i-M bit contains a pseudo-random code O, then the i-M bit does not overwrite information between registers 6 and 7,

In the third cycle of operation of the device, the signal from the first output (FIG. 10 of the control unit 9 transfers the memory block 4 to the recording mode and connects the register 3 outputs to the address inputs through the switch 2. Registrar 3. The signal from the second output of the control block 9 controls the contents of register 7 memory block 4 at the address stored in register 3. In the same cycle, a new pseudo-random source code 1 of pseudo-random codes is generated from the sixth output (Fig. 3) of control unit 9, and the pseudo-random code from the second group of its outputs is rewritten 3 are in register.

As a result of the termination of the operating cycle of the generator, the next output word of the generator was formed at the output of register 7, which in the next cycle will be converted in the described manner and written into memory block 4 at the address stored in register 3. The first group of outputs of source 1 of pseudorandom codes generated a new address for memory block 4. The process of generating the next output sets is then carried out by repeating the operating cycle of the generator. The source of the clock pulses is the sequence (Fig. Over), generated by the generator 12 clock pulses of the control unit 9.

Claims (2)

1. A pseudo-random binary sequence generator containing serially connected first register and second register whose outputs are connected to the information inputs of the memory block, the first and second control inputs of which are connected to the first and second outputs of the control block, the third output of which is connected with the installation of the first register, bus Start, connected to the input of the control unit, characterized in that, in order to extend the functionality by obtaining pseudo-random It contains the source of pseudo-random codes, the third register, the first and second switches, the block of AND elements, the block of OR elements, the outputs of which are connected to the synchronization inputs of the corresponding bits of the second register and first register, information the inputs of the bits of which are connected to the corresponding outputs of the second switch, the first group of inputs of which are connected to the outputs of the memory block, the address inputs of which are connected to the outputs of the first to mmutator, the first group of inputs of which is connected to the outputs of the third register, the inputs of which are connected to the second group of inputs of the first switch and the first group of outputs of the source of pseudo-random codes, the second group of outputs of which are connected to the first inputs of the elements And the block of elements And, the outputs of which are connected with the first inputs of the OR elements of the OR block, the second inputs of the OR elements of which are connected to the fourth output of the control block; the fifth output of which is connected to the second inputs of the elements AND block of the elec The second switch, the second group of inputs of which is connected to the outputs of the second register, the output of the control unit, is connected to the control input of the third register and the first input of the source of pseudo-random codes, the second input of which is connected to the third output of the control unit, the first output of which is connected to the input of the first switch. 2. The generator according to claim 1, wherein the control unit comprises a clock pulse generator, an initial setup circuit trigger, four AND elements, a shift register, three OR elements, the first inputs of which are connected to the input of the control unit and the first trigger input, the output of which connected to the first input of the first element And, the output of which is connected to the first inputs of the second, third, fourth elements And and to the synchronization input of the shift register, the corresponding outputs of which are connected to the second inputs of the second, respectively the second and fourth elements AND, the output of the second element AND. is connected to the second input of the second OR element and the first OR element, the third input of which is connected to the output of the fourth AND element and the second input of the third OR element, the output of which is the sixth output of the control unit, the third output of which is connected to the second input of the trigger, the first output of the initial setup circuit, the control input and the second information input of the shift register, the first information input of which is connected to the output of its last bit and the first the second output of the control unit, the second, fourth and fifth outputs of which are, respectively, the outputs of the first, second OR elements and the third element AND, the output of the clock generator is connected to the second input of the first element AND, the second output of the initial setup is connected to the third information input of the register shear. Compiled by Y. Burmistrov M. Khodanych proofreader I. Muska 4834/55 Circulation 816 Subscription VNIIPI State Committee on the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Projectnang q} U2.Z physical