SU1244727A1 - Device for checking semiconductor internal memory - Google Patents

Abstract

The invention relates to computing and can be used for the functional control of operational memory chips. The aim of the invention is to increase the reliability of the control. The device contains a clock signal generator, an address counter, a cycle counter, a sub-cycle counter, comparison blocks, a start-stop unit, an OR-NOT element, and UNIMNATIBILITY elements. The device implements four control sub-cycles that form a complete cycle: writing the test sequence to the memory, reading it from the memory, writing the inverted test sequence to the memory, reading the last memory, 3 slug. c (L C H fe 4; a 4 1C

Description

The invention relates to computing technology and can be used for the functional control of operational memory chips (RAM),

. The purpose of the invention is: elevation. accessibility control.

FIG. 1 shows a functional diagram of the device; in fig. Figures 2 and 3 are diagrams explaining the operation of the device for monitoring, for example, two-address RAM.

The device contains a generator of 1 clock signals, a counter 2 addresses, a counter of 3 sub cycles, a counter of 4 cycles, an OR-NOT 5 element, the first 6 and second 7 comparison blocks, the indication block 8, the elements 9, -9, UNABILITY and the start-stop block 10 (n - counter size 2). FIG. 1 shows a verifiable memory 11; in fig. 2 - diagrams of signals 12 at the output of the lower bit of the counter 2, signals 13 at the output of the lower bit of the counter 4, signals 14 at the output of the first element 9, HEPABHOBHAi BUSES, signals -15 at the output of the higher bit of the counter 2, signals 16 at the output the most significant bit of the counter is 4 cycles, signals 17 at the output of the second element 9u INCOMPENSITY, signals 8 at the second input of the comparison unit 6; in fig. 3 - diagrams of signals 19 and 20, respectively, at the second and first inputs of comparison unit 6, test sequence. the accuracy of the recording signals 21. at the output of the comparator unit 6, the diagrams of the signals 22 from the low-order output of the counter 3, the diagram 23 of the complete control cycle; in fig. 3 and 4 denote time axis t.

The device works as follows.

When the device is operated, the verifiable on-line semiconductor memory 11 (Fig. 1) stores the sequentially entered information in the order it arrives and displays the information sequentially in the order determined by the order of recording this information.

The device implements four sub-cycles of control, forming a small cycot of control — writing a test sequence to the memory; reading the test sequence; writing the inverted test sequence to memory; reading the inverted test sequence from memory.

Before operation, counters 2-4 are in the zero state. When the Start command is started, the block 10 starts the generator 1, which starts pulsing the clock to the input, the block 8 and the counting input of the counter 2 With the installation of counter 2 in I, the cycle starts

control dough. All counters 2-4 work in continuous-recalculation mode.

Counter 2 forms the address code at which the cell is being accessed, the memory to be scanned, which is fed to the first inputs of the corresponding elements 9 UNEQUAL VALUE, the second inputs of which receive the code. from the output of counter 4. Overflow of counter 2 means the end of one subcycle.

The overflow pulses of counter 2 are counted by counter 3, the overflow pulses of which are counted by counter 4. Overflow of counter 4 means the passage of one large control cycle.

The lowest bit of counter 3 generates a code that provides the implementation of the RECORDING and READING modes (O - RECORDING, 1 - READING) information for the monitored memory.

In the RECORDING and READING modes, counter 2 forms identical address sequences. Unit 6 generates a test sequence of pulses, received both at the information input of the monitored memory 11 for recording and at the second input of the block, at the first input of which the information read from the monitored memory is fed. Block 7 is used to compare the data read from the scanned memory at specified address sequences to data written at the same addresses.

The detection of a mismatch of codes recorded and read from the memory indicates the presence of a fault (for example, the presence of a constant 1 or 0).

If it coincides for the entire cycle of control of the recorded and read information, the next cycle of writing and reading is carried out. Such; writing and comparing reveals the mutual influence between the cells of the monitored memory. In addition, it is possible to detect address circuits that are in a constant O or I state, and short-circuited address circuits. In the case of faulty circuits in individual cells, the data will be written to other memory cells, which is revealed in the subsequent read cycle.

According to the results of the comparison, in block 7 of the recorded and read information, a GODEN-BRACK signal is generated, which from the output of block 7 goes to block 8, where a failure or failure is recorded and the STOP signal is generated at which the device stops forming a test sequence.

Thus, this device makes a test control of the interconnections between the address chains and the bits of the memory cells with a modified dynamic test such as running I or O.

For example, during the first small cycle (Fig. 3-21) in the first subcycle, 1 is written to the first address, O is written to all other addresses. During the second subcycle, the recorded information is read. During the third subcycle, the recorded information is inverted; O is written to the first address, and G. to the other addresses. In the fourth subcycle, a combination of the recorded information occurs.

In the second minor cycle, in its first subcycle it is recorded at the second address 1, and for the rest, O. Then the information in the second subcycle is read. In the third subcycle, O is written to the second address, and 1. to the other addresses.

In the third minor cycle, in its first subcycle, it writes to the third address, and to the others, O.V., the third subcycle, writes to

Ui tl

the third address is Oh and the rest

I

In the second and fourth subcycles, the recorded information is read.

In the fourth minor cycle, in the first subcycle there is a record of 1 in -, the fourth address, and in the rest; o. In the third subcycle, O is written in the fourth, and in the others - 1. At the end of the fourth sub-loop.

,

.

ten

15

20

25

thirty

35

40

45

50

55

la ends the full control cycle.

Thus, in this particular case, the control cycle includes four small cycles, and in the first two subcycles there is a test of the runner type test 1, and in the third and fourth subcycles, the test run O takes place (Fig. 3-21, and 22 );

Claims (1)

Invention Formula A device for monitoring semiconductor RAM, containing an address counter, a cycle counter, first and second comparison blocks and a start-up block, the first output of the CATO is connected to the reset input of the address counter, the first input of the second comparison block being that, in order to increase the reliability of the control, a clock signal generator, a sub-cycle counter, the UNEQUAL VALUE element, a display unit and an OR-NOT element, whose inputs are connected to the outputs of the HEARCH elements ACCURACY, and the output is connected to the first input of the first comparison unit, the second input of which is connected to the high-end output of the sub-cycle counter, the start input of which is connected to the overflow output of the address counter, and the reset input is connected to the first output of the counter-start unit cycles, the start input of which is connected to the overflow output of the counter of sub cycles, the first inputs of the elements UNEMBILITY are connected to the outputs of the address counter, and the second inputs are connected to the outputs of the cycle counter, the overflow output of which It is connected to the first input of the start-stop unit, the first output of the clock signal generator is connected to the start input of the address counter, and the second output is connected to the first input of the display unit, the second input and output of which are connected to the second output and to the second input of the start-up unit stop, the third output of which is connected to the input of the clock signal generator, the third input of the display unit is connected to the output of the second comparison unit, the second input of which is connected to the output of the first comparison unit, the output of the low-order counter of subcycles is ts 512447276 the control output of the device, the counter outputs responsibly address and information output addresses and the output of the first block of which moves is a comparison. -PPP PP L PP J1, P P J -a-g.  ./Shch 1TsGPShPi11Sh P1.    i Cyc / f g ontrol Fig.Z Compiled by V, Gordonova Editor I. Casarda Tehred I. Popovich Corrector E. Sirohman Order 3924/55 Circulation 543Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d, 4/5 Production and printing company, Uzhgorod, st. Design, .4