SU1243113A1 - Device for synchronizing pulses - Google Patents

Abstract

The invention can be used for temporal coupling of signals in devices for processing, converting and transmitting information. The purpose of the invention is to increase the reliability of work. The device contains D-triggers 1 and 2, inverter 3 and. tires 6-8 clock pulses, output and clock pulses, respectively. Introduction to the device of the synchronous driver of 4 pulses, the driver of 5 short pulses ensures synchronization of signals without distorting the output pulse sequence, regardless of the phase ratio of the synchronous pulses (oh and clock sequence. 2 or tSD 4 CO

Description

The invention relates to a pulse technique and can be used to temporarily lock on signals in devices for processing, transforming and transmitting information.

The purpose of the invention is to increase the reliability of operation by eliminating the possibility of distortion of the frequency of the output pulses.

FIG. 1 shows an electrical functional diagram of the device in FIG. 2 - time diagrams that show his work.

The device for synchronizing pulses contains two triggers 1 and

2, each of which is D-type, inverter 3, synchronizer driver 4 pulses, driver 5 short pulses, the input of which is connected to bus 6 of synchronized pulses, the output from the K input of the first trigger 1, C input of which is connected to the forward output the second trigger 2 and with the output bus 7,. In the first and second triggers 1 and 2 are connected to the logic unit T., the inverse output of the first trigger 1 is connected to the first input of the synchronous driver 4 pulses, the second input of which is connected to the bus 8 clock pulses and through the inverter 3 is connected to the R-input of the second trigger 2. The C-input of which is connected to the output of the synchronous driver of 4 pulses.

The synchronous driver of 4 pulses contains a D-flip-flop 9, the D input of which is the first input of the synchronous driver of 4 pulses, the C input of the second input of the synchronous

the pulse driver, the R input through delay element 10 is connected to the direct output of the D flip-flop 9, which is the output of the synchronous driver 4 pulse.

The device for synchronizing pulses works as follows. After applying pulses to the bus 8 (Fig. 2o), the triggers 1 and 2 are set to the initial state, the trigger 1 - to the single state, the trigger 2 - to the zero state.

With the arrival of an impulse to the bus 6 (Fig. 2b), the trigger 1 is set to the zero state along its front (Fig. 2S), and the logical level is removed from its inverse output

five

0 o 5

0

five

1 (Fig. 2d) 5 arriving at the first input of the former 4. On the front of the first clock pulse at the output of the former 4, a short pulse appears (Fig. 2), the front of which in the trigger 2 records the level of logic G, .ii on the R-input trigger 2 logic level O allows the trigger (Fig. 2x).

At the output of trigger 2, the beginning of the pulse appears, the duration of which is decelerated by the duration of the clock pulse, since with the end of the clock pulse, the R input of trigger 2 through the inverter 3 (FIG. 2e) receives a logic level 1 and trigger 2 is set to zero state.

The front of the pulse from the output of the trigger 2 to the trigger 1 records the level of logic 1, after which the device is ready to receive the next pulse on the bus 6.

Thus, the proposed device provides synchronization of signals without distorting the output pulse sequence, regardless of the phase ratio of the pulses of both the synchronized and clock sequences.

1 At the output of the device, the first clock pulse that arrives on the bus 8 after the arrival of the synchronized pulse on the bus 6 is unambiguously allocated.

Claims (1)

Formula invented A device for synchronizing pulses, containing two triggers, each of which is D-type, the D input of the first of which is connected to the bus of a logical unit, an output bus that is connected to the direct output of the second trigger, a clock bus connected to the input of the inverter, and synchronous pulses bus, which is distinguished by the fact that, in order to increase the reliability of operation, a synchronous pulse driver, a short pulse driver, whose input is connected to a clock pulse bus, and an output are inputted to it Vågå trigger, S-input coupled to a direct output of the second flip-flop, D-input of the latter is connected with the bus logic unit, R-input - with the output of the inverter, C-input - with the output of the synchronous pulse driver, the first input 12431134 Which is connected to the inverse output of the first trigger, the second input is connected to the clock pulse bus. a 5 6 gde FIG. 2