SU1242956A1 - Interface for linking microprocessor system with peripherals with check - Google Patents

Abstract

The invention relates to microprocessor technology and can be used in the design of microprocessor systems and microcomputers with high reliability indicators. The aim of the invention is to increase the reliability of the device by controlling the response time of the addressed external device. In the event of a failure of an external device, the interface device switches the next external device. The device contains an encoder, an asynchronous communication unit, an address adder, a request analysis unit, two buffer registers, a wait cycle time counter, an address counter, a decoder. Control trigger, two blocks of AND elements, three AND elements and two OR elements, 3 w1., 2 tab. (L yu sd od

Description

f1

The invention relates to microprocessor technology and can be used in designing 1-1 and micro processor 1 systems and micro computers with high reliability indices.

The aim of the invention is to increase the nk-e reliability of the device by controlling the response time and the addressed external device.

FIG. Figure 1 shows the functional diagram of devices for interfacing a microprocessor system with external devices with control; in fig. 2 is a diagram of an asynchronous communication unit; in fig. 3 - block diagram analysis of requests.

The device (Fig, 1) contains the encoder 1; block 2, asynchronous communication, adder 3 addresses, block 4 analysis requests, the first and second buffer registers 5 and 5, respectively, the counter 7 of the waiting cycle time, the counter 8 addresses, the decoder 9, the trigger

10 controls, first and second blocks

11 and 12 elements AND, respectively, perzj - the third elements AND 13-15 respectively, the first and second elements OR 16 and 17 respectively 5 output

i 8 microprocessor data, microprocessor address output 19, cycle timing synchronization output 20 i niKponoprocessor, first and second outputs 21 and 22, respectively, of the system clock generator, output microprocessor output resolution 23, parvm to sixth outputs of the encoder, respectively 1, the first output 30 of the asynchronous cpu 2 unit, the first input-output 31 of the 2 asynchronous communication, the first input-output 3 of the asynchronous communication unit 2, the second output 32 and the second input .33 of the asynchronous communication unit 2, the first and second inputs 34 and 35, respectively, block 4- a request availability, input 36 of block 4 av: request request, output 37 of the non-malformed external device, device failure output 38, device ready signal output 39, system interface trunk interrupt request output 40, microprocessor interrupt input 4.

The asynchronous communication unit 2 (Fig. 2) contains the first and second delay elements 42 and 43, respectively, the first - the third triggers 44-46, respectively, per-m - the third

6 . 2 main amplifiers 47-49, respectively, and the first - the third elements And 50-52, respectively. .

Query analysis unit 4 (FIG. 3) contains a delay element 53, a control trigger 54 and an P1 element 55.

The device works as follows.

At the beginning of each JAC computer microprocessor cycle to external devices in cycle T, the microprocessor generates a SYNC synchronization signal at output 20, which sets the control trigger 10 into a unit and generates a synchronization signal of the first buffer register 5. This results in writing the processor state word code in register 5, in the same clock at the output of the 19 microprocessor

the address code of the external device being accessed is set. At the output 39 of the device, a zero readiness signal is set. The code of the state word: the processor from register 5 is fed to the input of the encoder 1, and a single signal is set at one of its corresponding outputs. In addition, after | transfer of the trigger 10 into a single state; the asynchronous communication unit 2 in the case of CUSTOMER communication with the selected external device generates an execution signal (IDP) at the second output 32. According to the IDP signal. addressable external device issues. the response signal (ATV) to the asynchronous communication unit 2. At the same time, in the considered device, after allowing the issuance of the signal to the IDPs, countdown of waiting time is carried out. This mode is carried out by recording a series of clock pulses in counter 7. The number N of pulses corresponds to the response; in other words, the response time of the addressed external device to the request. If from the VN: the latest device comes within the allowable time of an OTB 5 bank, then the time count in counter 7 is terminated by setting it to zero. In this case, if the addressable external device is functioning correctly, the contents of counter 8 are equal to zero. Modification of the address by adder 3 is not performed.

The operation of the encoder 1 is described by the correspondence table (Table),

The values of the input signals, encoder 1 and the values of its output signals at outputs 25-29 unambiguously correspond to the codes of the processor state word (PSW) during the following cycles: MEMORY READ, MEMORY VffilTE, INPUT, OUTPUT, INTERPUT of the microprocessor K 580 series (INTEL sos A)

in the event that the signal OTV from the addressed external device does not arrive at the set (maximum) time, then with the arrival of the (N + l) -ro pulse at the overflow output of counter 7, a single signal is generated, which is recorded in counter 8. Therefore, the microprocessor in This case enters the Standby mode. Formed in the counter 8 by the code 00., .01, the address of the external device is modified. The modification operation is performed by the adder 3 addresses. Modifications are made to the higher bits of the address code by incrementing this code by one. As a result, the kotz address of the next external device is generated. In this case, the trigger 10 does not return to the initial state, but remains in a single state, which makes it possible to re-execute the count of the waiting cycle time. If the TTV signal arrives within the set time, then j also has a waiting mode (cycle) to the falling edge of pulse 4, it goes out of standby mode and continues to work. Otherwise, the contents of counter 8 are incremented by one more and the code 000 ... 10 is in it. As a result

Table

I

An address modification operation occurs and the address code of the next external device is generated. All the time after recording the information, the corresponding code is formed in the counter 8 at the output 37 of the device. In case of failure of all external devices, after the failure of the last of them, a failure signal is generated at the output 39 of the device.

The operation of the adder 3 addresses when modifying the address of the external device can be described by the correspondence table (Table .. 2),

table 2

00000000 00101101 00111101 o l 000000

00000000 00110101 01000101 01001000

From table 2 match adder 3 addresses, it follows that the modification

The address with the zero content of the counter 8 addresses {during the correct operation of the external devices being addressed) is not implemented.

The asynchronous communication unit 2 functions as follows.

In the initial state, the triggers 44-46 are in the zero state. With the arrival of the control signal from trigger 10 and in the absence of blocking from block 4, element I 50 triggers and sets trigger 44 to one state. In this case, the signal for busy line (ЗМА) is outputted to the interface trunk, and the control signal encoder 1 - an enable signal, through which it sends one of the control signals to the interface highway.

After a time L ,, (the response time of the first delay element 42), the trigger 45 is set to one. condition. At the output 32 of unit 2, the signal of the VGS is set, and, in addition, the second element AND.5 is opened at the first input. When a single signal arrives at the input 33 of block 4 (signal of the FCV), the trigger 46 is set to the single state. In this case, a single signal is supplied to the third output of block 2 and to the input of the second delay element 43. Through time t. (the response time of the second delay element 43), the trigger 45 is set to the zero state. The third element And 52 opens at the second entrance. After the VS1 signal has been removed from the input 33 of the unit 2, the trigger 46 is set to the zero state. This causes the first trigger 44 to be set to zero, which produces a removal of the main line capture signal from output 31 of block 2. In this case, the encoder 1 disconnects the information, address and control signals from the interface highway. The cycle of operation of block 2 ends there.

Unit 4 analysis of access requests from the highway works as follows.

An external device, which requires access to the interface trunk, generates a request for access to the trunk, which is fed to the first input 34 of block 4. In the absence of a signal.

0

s

0

five

0

i

allowing access to the highway, which arrives at the output of block 4. The external active device, having received the signal to enable access to the highway, responds with a request confirmation signal, which is fed to the input 35 of block 4.

This signal is fed to the S-input of the trigger 54 and to the input of the element 53 of the delay. Element And 55 resets the access enable signal. Nu. The left signal from the zero output of the trigger 54 is fed to the first output of the block 4, blocking the operation of block 2 to use the interface line device.

After resetting a single signal from input 35 of block 4, after time f jj (time of operation of the delay element 53), the trigger 54 is set to the initial (zero) state.

The device for interfacing the microprocessor system with external control devices operates as follows.

In the initial state, all the memory elements are in the zero state. (Circuit set to zero conditionally not shown) In n: the start of each machine cycle, the microprocessor generates a sync signal SYNCj which is output to the microprocessor output 20. In kahsdom microprocessor tact, the outputs 2 and 22 of the device become a sequence of pulses H and 2, respectively.

When executing a program in the first cycle of each machine cycle, except for setting the SYNC signal at the sync cycle output 20 of the microprocessor operation, the processor status word code is set at the microprocessor data output 18, and the external device address code is output at the microprocessor output 19 when performing receive operations, IRM, and transmitting VDP information to / from the addressable peripheral device). When SYNC signals appear at the output 20 of the microprocessor and pulse f at the output 2 of the system clock generator at the output e AND gate 13 for- truets single signal. As a result of this, the trigger 10 goes to one state, and the register of the processor state word is written to register 5.

The microprocessor state signals are fed to the inputs of the encoder 1 from the output of register 5. From the zero output of trigger 10 to the output 38 of the device, a signal of unavailability (zero signal) is received. From the single output of the trigger 10, the unit 2 of the asynchronous communication receives a single signal, which indicates that the microprocessor is required to exchange information with an external device. Using this signal, the asynchronous communication unit 2 analyzes the logical condition (the presence of signals from the interface bus busy and confirmation of the trunk request, respectively). The fulfillment of this condition indicates that the interface trunk is not occupied, i.e. other active devices (external devices) connected to the trunk are not currently exchanging information and not permitting the use of the trunk. If the given condition is fulfilled, the asynchronous communication unit 2 generates a single signal at the input-output 31 (ЗМА) and at the first output 30, which initiates the operation of the encoder 1.

A single signal from the output 30 of the asynchronous communication unit 2 produces the opening of the element 14 at its third input, at each operation cycle of the device with the arrival of pulses from the output 21 of the system clock generator in the counter 7, the counting operation of the number of pulses is performed ( determination of the duration of the waiting cycle),

Cipher I in. Depending on the value of the code of the state word processor, coming from the output of the register 5, it produces one of the control signals inserted into the system interface bus, and also connects the address signals to the address bus addresses of the interface highway. In addition, in the Record or Delivery mode (HALL, VDCH), data signals are connected to the buses of the interface bus, and in the Read or Receive (CTN, PFP) modes, the information input of the register 6 is connected to the buses of the interface highway. | the asynchronous communication unit 2 carries an IDP signal at the second exit 32. By this signal, the addressed

the peripheral device or memory device in the Record and Issue modes, respectively, receives information and responds to the GTV signals. In the modes of Reading and Reception, information signals are sent to the buses of the interface highway, and they are transmitted by an OT signal.

Upon receiving the signal of the OTF, in the case of correct functioning of the addressed external device, a single signal is generated at the third output of the asynchronous communication unit 2 and is fed to the second inputs of the first and second elements OR 16 and 17 respectively. As a result, the trigger 10 goes to the zero state and the Ready signal is generated at the output 39 of the device. In addition, on this signal, the counter 7 of the standby cycle time is set to zero and the zero state of the counter 8 of the address is confirmed. In the Read and Receive modes, information is recorded in the TSS signal. In register 6. After receiving the TSS signal, after a time required to enter information into register 6, the asynchronous communication unit 2 resets the IDP signal. The external device on resetting the IDP signal responds by resetting the signal of the TSS. Block 2 of asynchronous communication. After resetting the signal, disconnects the signal of the SMA, as well as the address, information and control signals from the interface trunk. In case the interface line turns out to be closed when the microprocessor accesses the external device, a single signal is not generated at the first output 30 of the asynchronous communication unit and thus the AND 14 element remains in the Closed state. The counting time of the sleep cycle in counter 7 is not performed. From the zero output of the trigger 10 to the output 38 of the device receives a zero signal. On this signal, the microprocessor enters standby mode for a while until the system's interface trunk is released.

If the mode of information exchange between the microprocessor and the addressed external device can be set, but the signal of the OTB from it will not come after time 1 (after the arrival of the N-ro pulse on

counter 7) with the arrival of (N + l) -ro pulse at the output of counter 7, an overflow signal is generated, which is fed to the counting input of counter 8 In this case, the unit code is set in counter 8. According to the content code of the counter 8 in the adder 3, the address code of the addressable external device is modified. The address is modified by incrementing by one the address code of the external device. At the same time, the monitoring of the expectation cycle duration continues. . The counter 7 records the synchronization pulses H.

If the signal of the TSS arrives within the allowable time, the operation of the device proceeds according to the described algorithm. .

In the event that the second addressable external device does not generate the signal OTV within the set time, a second change occurs in the contents of the counter 8. It contains the code two. This code is used to modify the address code of the external device by increasing by two the original code of the address of the external device.

If a failure occurs in all external devices, then after writing the L-th unit to the counter 8 and after the time i has elapsed, the output 39 of the device has a failure signal.

The microprocessor interrupt is organized as follows.

An external device, which requires interruption of the program, transmits an interrupt request signal to the interface trunk via the DPR bus. In the device, this signal is transformed to the PEPP input of the microprocessor. After executing the next command, the microprocessor perceives the PEPP signal (if the PEPP input is not blocked) and during the call for the next command in the "status word code" sets the acknowledgment signal of the interrupt request P. ZP. PRER. The encoder 1 in this case generates a signal of the RPR at its sixth output 29. The signal of the RPR passes sequentially through all the initiative peripheral devices. The nearest peripheral device, which raised the interrupt request, receives the RPR signal, blocks its further passage and issues the code of the interrupt vector to the interface trunk, accompanied by its OTV signal.

Thus, from the device operation algorithm for matching

Neither the microprocessor system with external devices with control follows that it controls the response time of the addressed external device and, in the event of a failure, it controls the switching of the next external device.

Claims (1)

Invention Formula A device for interfacing a microprocessor system with external devices with a control, comprising an asynchronous communication unit, a request analysis unit, an encoder, first and second buffer registers, first and second blocks of AND elements, a control trigger, and the first AND element, with the microprocessor data output connected to . the information input of the first block of alements And and the information input of the first buffer register. The output of the first block of elements I is connected to the information bus of the system interface bus and the information input of the second buffer register, the output of the first buffer register is connected to the information input of the cipher. and the third bits of the first output of which are connected to the control inputs of the first and second blocks of elements AND AND E1 input resolution of the second buffer register, respectively, and the second oh - the sixth outputs of the encoder are connected to the read, write, receive, output and enable busses of the system interface bus interrupt, the output of the second buffer register is connected to the microprocessor data bus, the first group of address bus address bits of the scrocessor is connected to the corresponding bits of the information input of the second block of elements And whose output is connected with the address bus of the interface trunk of the system, the first output of the asynch link unit is connected to the building input of the encoder, input-output 11 the acHHXpoHiioti SVUPN block path is connected to the 1S-interlace system's signal bus, the first input of the asynchronous communication unit is connected to the first output of the query analysis unit, the second output of which is connected to the access bus of the interface backbone of the system, the second output of the asynchronous link The zi is connected to the system interface bus, the second input of the asynchronous communication unit is connected to the system interface line response bus, the first and the second request analysis block are connected to the query bus stupa and confirmation of the request of the system interface bus, respectively, the microprocessor cycle synchronization output is connected to the first input of the first element, the first synchronization output of the system clock generator is connected to the second input of the first element And, the output of which is connected to the S input of the control trigger and the synchronization input of the first buffer register, a single control trigger output is connected to. the third input of the asynchronous communication unit, zero the control trigger output is the device readiness output, the microprocessor information receive enable output is connected to the synchronization input of the second buffer register, the system interface trunk interrupt request bus is connected to the microprocessor interrupt input, characterized in that increase the reliability of the device by monitoring the response time of the addressed external device; it contains the wait cycle time counter, the ad counter 2429S61 rez, address ch.chmator, decoder, iiepisbiii and the second element OR, the second and third elements AND, the first synchronization output being so 5 of the system generator is connected to the first input of the second element I, the output of which is connected to the counting input of the timer of the waiting cycle, the output of which overflows 10 with the counting input of the address counter, the information output of which is connected to the input of the decoder and the first input of the address adder, the overflow output of the address counter is connected to 15 output device failure and the first inputs of the first element OR and the third element And the second clock output of the system clock generator is connected to the second input of the third 20 of the AND element, the output of which is connected to the first input of the second OR element, the output of which is connected to the installation input of the address counter, the second group of address bus of the micro25 processor bus is connected to the second input of the totalizer address, the output of which is connected to the corresponding bits of the information input of the second block elements And, the third output of the block 30 asynchronous communications are connected to the second inputs of the first and second OR elements, the output of the first OR element is connected to the R input of the control trigger and the installation input of the sleep cycle time counter, the output of the decoder is a display output number of the failed external device, the single output of the control trigger is connected with the second entrance 40 of the second element And, the third input of which is central to the first output of the asynchronous communication unit. fig.Z