SU1226633A1 - Device for generating pulses in the middle of time interval - Google Patents

Abstract

The invention relates to automation and measuring equipment and can be used in information processing and conversion devices. The purpose of the invention is to expand the functionality achieved by means of forming a pulse in the middle of the time interval and the possibility of changing the position of this pulse within the time interval relative to its middle in a wide range of frequencies and equipments. To achieve this goal, a subtracting 7 and a summing 8 pulse counters, a trigger 4, a NOT 6 logic element, an adder 9 and a comparator 2 are entered into the device. In addition, the device contains an input bus 1, a clock generator 3, a delay element 5. The device operates according to This is shown in the time charts in the specification. 2 Il. i (L Fi2. /

Description

The invention relates to automation and measuring technology and can be used in devices for processing and transforming information, and when carrying out analogous digital conversions based on the principle of fixing output signals for conversion time, it is possible to use fixing devices in the middle of the time interval

The purpose of the invention is to expand the functional capabilities of the device due to the pulse fflpovaniya pulse in the middle of the time interval and the possibility of changing the position of this pulse within the time interval relative to its middle in a wide frequency range and borehole

Fig. 1 shows a structural electrical circuit of a pulse forcing device in the middle of a time interval 5 in Fig. 2 - time diagrams

The device contains an input bus 1, a comparator 2, a generator of 3 clock pulses, the trigger element 5 delay, the element NOT 6, counters 7 and 8 pulses and the adder 9,

In the diagram (fig. 2) are marked; And the output signal of the generator is 3 clock pulses, B - sigv: al at the output of comparator 2, C - signal at the direct output of flip-flop 4 (rewriting signal) j D - signal at the output of delay element 5 (zero signal), D high-level device signal ( signal output transfer subtractive counter 7),

The device works as follows.

A periodic signal, for example, a sinusoidal signal, is fed to the device input bus 1. Passing the comparator 2, the signal is converted into a sequence of pulses, the distances between which determine the measured time intervals (Figo 2B) 5 and on the front of the front of these pulses by trigger 4 and the element do NOT generate pulses to control the rewriting of the subtracting counter 7 (Fig , 2 V) and the reset signal of the summing counter 8, n creating a certain delay of the reset pulse relative to the rewrite pulse serves as a delay element 5 (FIG. 2 D). This ensures first the overwriting of the contents of the summing

the counter to the subtractor and only then the resetting of the summing counter. The counting inputs of both counters are connected to the generator 3 clock output.

pulses (Fig. 2A). The counters are designed in such a way that when there is a logical unit at the transfer input, the counting is prohibited, and the control over the rewriting input and the zeroing input is maintained. Thus, after the arrival of the pulse front from the comparator 2 to the trigger synchronization input and the transfer inputs of counters 7 and 8, the counting stops, overwrites

the contents of counter 8 into counter 7 and resetting counter 8. When the cutoff pulse, Toe, arrives from the comparator output, the new measured interval 5 begins, the counters are ready for counting.

At the end of each measured interval t in the counter 8 there is a recorded number n corresponding to the number of periods of the frequency of the oscillator 3 clocks placed in this interval

l

 T

The counters of the counters 7 and 8 are the same and are determined by the maximum duration of the input signal t and the pulse repetition period t of the clock frequency generator 3. In this case, the minimum distance between

measured intervals equal to

T 1 + „,

MII 1 2

BUT

where L, pulse rewrite duration,

 - ,,., is the pulse width of the zero setting.

The parallel output of the counter 8 soy ,, is dinin through the adder with the parallel input of counter 7 with a shift of one bit towards the younger so that the N-bit of the output is connected to (N-1) - the input bit, respectively. Therefore, at the arrival of a rewrite pulse, formed at the end of the measured interval, the counter 7 records the number from the counter 8, equal to

p p / 2.

At the end of the time interval, the caster 8 zeros, and the counter 7 contains a number that uses 31

c to fix the middle of the new time interval.

Thus, at output 10 (transfer of counter 7) of the device in real time at the time of passing through the middle of the time interval, a short pulse of duration T is formed.

When changing the frequency or duty cycle of the input signal, the fixation of the middle of the next time interval is produced with a relative error determined by the formula

l N. (P; - P ;,)

1 - and-- - - --I

2 P. I

where n, n. is the number in the counter 8 after the termination of the i-ro and (i + 1) -ro intervals, respectively.

Correction of the position of the output pulse within the time interval relative to its middle occurs by an external command, arriving as a binary number at the input 11 of the correction (second input of the adder).

The device can be made on the 564 series microcircuits, the comparator is based on the 521SAZ microcircuit.

Claims (1)

Invention Formula A pulse shaping device in the middle of a time interval containing a clock pulse generator, a delay element, distinguishes i ту i 1 1-gtG-I h26633 This is so that, in order to expand the range of frequencies and portions while ensuring the possible expansion of the pulse position variation area within the time interval, subtractive and summing pulse counters, a trigger, an element NOT, an adder and a comparator, whose input connected to the device's jQ input, and the output to the transfer inputs of both counters and the trigger synchronization input, the information input AND input of the installation of which is connected respectively to the power bus and the total thickness of the device the trigger output is connected to the input of the delay element and the input of the element NOT, the output of which 20 25 connected to the setup input of the zero trigger, the direct output of which is connected to the rewrite input of the subtracting pulse counter, the counting input of which is connected to the output of the clock generator and to the counting input of the pulse adding counter, while the N-output of the adding pulse counter is connected via an adder with (NI ) -M input subtractive pulse counter, respectively, and the transfer output The 30 subtractive pulse counter is the output of the device, and the second parallel input of the adder is the correction input, the position of the output pulse within the time interval, and 35, the output of the delay element is connected to the zeroing input of the summing counter. FIG. 2