SU1226624A1 - Pulser - Google Patents

Abstract

The invention can be used in information processing devices. The purpose of the invention is to increase the speed and reliability of operation. The device contains JK-trigger 1, element 2 delays, elements OR-NOT 3 and 4, element OR 5, input bus 7 and output bus 6. Achieving this goal is promoted by the introduction into the device of the element OR-HE 4 and the formation of new connections between its elements. The description contains timing diagrams for how the device works. 2 Il. 7

Description

Ф14г.1

The invention relates to a pulse technique and can be used in information processing devices.

The purpose of the invention is to increase speed while increasing reliability.

FIG. 1 shows the electrical functional scheme of the device; in fig. 2 - time diagrams, in accordance with his work.

The pulse shaper contains a 1K-trigger 1, delay element 2, SHI-NOT 3 element, additional element 4, OR 5 element, the output of which is connected to the output bus 6, the first input - to the direct output 1K of the trigger 1 and the delay element 2 whose output is connected to the second input of the element OR 5 and to the first input of the element OR-NOT 3., the second input of which is connected to the inverse output of the 1K-trigger 1, the K-input of which is connected to the output of the element lifW-HE 3, 1-input - with the output of the additional element 4, the first input of which is connected to the input bus 7 5 second vhed - with the release of the element. OR 5 o

The pulse shaper operates as follows with

In the initial state at the direct output of the trigger 1 (Fig. 2 &), at the output of the delay element 2 (Fig. 2 g), and the output of the ShZh 5 element (Fig. 26) {output bus 6, at the output of the element 3 (Fig ., And the input bus 7 () has a logic level; sky O, at the input of element 4 and the inverse output of flip-flop H - the level of logic 1. When an input pulse arrives at the input bus 7, the output of element 4 (FIG. 25) appears the logic level is O, which ensures that trigger 1 is set to one state. The logic level 1 s. of the direct output of Tpnrfepa 1 is fed to the input of the element 2 delays and a second input of element 5, which ensures the appearance of a logic level 1 at the output of element 5 and a logic level O at the output of element 4

At the same time, the logic level O from the inverse output of flip-flop 1 is fed to the first input of element 3,

0

3

at the same time, logic level 1 appears at the output of this element, which ensures that trigger 1 is prepared for a reset. After the time t ,, equal to the delay time of the delay element 2, a logic level 1 appears at its output, which confirms the presence of a signal at the output of element 5 and contributes to the appearance of a logical O at the output of the element OR-NOT 3, which ensures a reset trigger 1 to the zero state, i.e. prepares it to receive the next pulse from bus 7. At the end of the pulse at the output of delay element 2, the output of the element OR 5 is completed forming the output pulse.

Thus, at the direct output of flip-flop 1, a pulse with a duration equal to the delay time tj of the pulse by delay element 2 is formed, which, passing through delay element 2, ensures the formation at the output of the OR 5 element and bus 6 of a single pulse device with a duration Lj 2t Upon completion of the formation of the output pulse on bus 6 and the input pulse on bus 7, the enable level appears at the first input of trigger 1.

Claims (1)

Invention Formula The pulse shaper, the triggering device, whose direct input is connected to the first input of the OR element and the input of the delay element, the output of which is connected to the second input of the OR element, the output of which is connected to the output bus, the OR-NOT element and the input bus, - h and y w, and with the fact that, with a speed increase while simultaneously increasing reliability, an additional OR-NOT element is introduced into it, the output of which is connected to the 1-input of a 1K-type trigger, the first input - to the input bus , the second input - with the output of the element OR, the second input The one of which is connected to the first input of the SHSh-NOT element, the second input of which is connected to the inverse output r of the rigger, the K-input of which is connected to the code of the element OR NOT.