SU1205146A1 - Device for resistance computer - Google Patents

Description

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The invention relates to a computational technique, in particular to systems for controlling a computational process in a computer,

The purpose of the invention is to increase the speed of restarting the computer.

Figure 1 shows a block diagram of a device for restarting a computer; Fig. 2, a block diagram of the driver of control signals; Fig, 3 is a block diagram of the block fixing failure.

The device contains an encoder 1, a register of 2 addresses of micro-instructions, a block of 3 memory of micro-commands, a decoder 4, a trigger 5, a generator of 6 pulses, a counter 7, a driver 8 for controlling mjix signals and a block 9 for fixing the failure.

The signal conditioner contains a delay element 10, a one-shot P, a trigger 12, an element OR 13.

The block fixing failure contains one-shot 14, the counter 15 element is NOT 16, the element And 17,

The second input 1 of the F 1 is designed to receive an error detection signal. Counter 7 has three inputs: signal reception, signal enable, set to zero and one output. The purpose of generator 6 is to start the operation of the counter 7. The purpose of counter 7 is to start the driver 8 of control signals and the block 9 for latching the failure in case of signals from the generator 6 pulses and no signals at the installation input to zero of counter 7 and at the input of receiving counter signals 7

The imaging unit 8 has two inputs and two outputs, serves to issue the following signals: prohibition of receiving signals from counter 7 and requesting interruption of an.

The first input of the imaging unit 8 is connected to the output of the counter 7 and the input of the block 9 for latching the failure, the second input of the imaging unit 8 is designed to receive a signal that the standard of the power source of the computer is compliant.

The first output of the imaging unit 8 is connected to the signal enable input of the counter 7 counter, the second output

shaper 8 is connected to the first

: to the input of the encoder 1.

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Block 9 latching failure serves to alarm in case of sustained failure and the impossibility of restarting the computer without human intervention. The input of the failure-fixing unit 9 is connected to the output of the counter 7 and the first input of the driver 8, the output of the failure-fixing unit 9 forms the signal output of the device for restarting the computer,

In the driver 8 of the control signals, the input of the delay element 10, the input of the one-shot 11 and the synchronization input of the trigger 12 form the first input of the driver, the second input of which is formed by the first input of the element 13 OR, the output of the delay element 10 is connected to the input of the zero setting of the trigger 12, direct output which forms the first output of the imaging unit 8 and is connected to the input of the signal reception of the counter 7, the output of the one-shot 11 is connected to the second input of the element OR 13, the output of which forms the second output of the imaging unit 8 and connected to the first th input of the encoder 1.

The input of the failure-fixing unit 9 is formed by the input of the one-shot 14 and the input of receiving the signals of the counter 15 and is connected to the output of the counter 7 and the first input of the driver 8.

The output of the one-shot 14 is connected to the input of zeroing the counter 15, the first output of which is connected to the input of the HE element 16, the output of which is connected to the first input of the And 17 element, the second input of which is connected to the second output of the counter 15, the output of the And 17 element is the signal output devices for restarting a computer.

The device works as follows.

During normal operation of the computer in the control loop, the second input of the driver 8 receives a zero level of the wall, meaning that the nominal values of the computer power source are normal, the signal of the same level from the second output of the driver 8 enters the first input of the encoder 1, the second input of which also receives the signal zero level, which means no errors in the operation of the computer. At the single trigger input 5 interrupt signals are received from the timer, which is necessary

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when working in real time. At the direct output of the trigger 5, a single uro is set at the third input of the encoder 1, from the output of which the address of the corresponding micro-command is entered into the register 2 of the micro-command address, according to the contents of which the micro-command of the micro-memory unit 3 is inserted; teams. At the first output of the decrypted jpa 4, a signal for processing the interrupt from the timer occurs. This signal, arriving at the setup input to zero of trigger 5, resets it.

In the case of stopping the computational process, due to the occurrence of an error detection signal at the second input of the encoder 1, the address of the corresponding micro-command is entered into register 2 of the micro-command addresses, then this micro-command is read from the micro-memory block 3. As a result of the decoding of the microcommand, the second output of the decoder 4 receives a signal, signifying the transition to console mode due to an error.

In addition, if the timer fails or there is a malfunction that prevents the interrupts from the timer from being processed, the first output of the decoder 4 stops the generation of interrupt signals from the timer.

As in the case of stopping the computational process at the occurrence of an error detection signal, and in the event of faults resulting in the absence of interrupt processing signals from the timer, signals stop flowing to the input of the counter 7 to zero, the output of the generator 8 and the block is generated at its output 9 fixing failure. From the first output of the imaging unit 8, a signal is received to the input of the permission to receive signals from counter 7, prohibiting its further operation. At the second output of the imaging unit 8, a single-level signal is outputted to the first input of the encoder 1. A microinstruction is read out, which is used to output a general reset signal from the third output of the decoder 4.

Through the delay, determined by the installation time of the external device controllers of the computer, by the signal of

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reset, the zero level of the signal is restored at the second output of the control signal generator, the microcommand is combined, and the interrupt signal is output from the fourth output of the decoder 4. A program is called that allows the computer to restart the computer automatically and resume the computation process in the event of a fault. After the time required for restarting the computer, the driver 8 removes the prohibition signal, which from its first output came to the enable input of the signals from counter 7.

If a failure occurs, the computational process is restored. The block 9 for latching the fault is reset, not having time to work, from the first output of the decoder 4 the interrupt processing signals from the timer start to come to the inputs for setting the counter 7 and the trigger 5 to zero. The normal operation of the computer in the control loop continues.

In the event of a sustained failure and the impossibility of automatically restarting the computer to the input of the zero setting of counter 7, the arrival of the timer interrupt signal from the timer, the signal of prohibition from the first output of the driver 8 is removed from the signal enable input of the counter 7, which continue to receive signals signals from the generator 6 pulses. Consequently, the counter 7. generates a repeated signal, by which the block 9 of the latching of the failure is triggered, at the output of which an alarm is generated.

The shaper 8 operates as follows.

The signal from the output of the counter 7 is fed to the synchronization input of the trigger 12, sets it to one, triggers delay 10 and the one-shot 11. From the output of the trigger 12, the inhibit signal is fed to the input of the reception of the signals of the counter 7. The single-vibration P triggers a single level signal to the second input of the OR 13 element. In this case, the signal of a single level from the output of the element OR 13 is fed to the first input of the encoder 1, which as a result causes the appearance of a normal reset signal on the third output of the decoder 4. Then the level c ignals at the output of the element OR 13, follows5

The first input of the encoder 1 restores a zero value, and as a result, an interrupt signal is output from the fourth output of the decoder A, to. which causes the program to automatically restart the computer in the event of a failure. After the time required for the computer to automatically restart, the signal from the output of the delay element 10 is fed to the input of the zero setting of the trigger 12, resetting it. From the output of trigger 12, the zero-level signal enables the operation of counter 7.

In the event of a deviation from the norm of one of the nominal values of the power source of a computer, the signal of a single level arrives at the first input of the element OR 13 and therefore at the first input of the encoder I. As a result, a general reset signal is output from the third output of the decoder 4.

When the supply voltage is restored, a zero level signal is applied to the first input of the {{13) element. At the same time, at the output of the element .IL 13 and, therefore, at the first input of the bus | | rator 1, the signal level changes from one to

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zero and, as a result, outputting an interrupt signal from the fourth output of the decoder 4, on which a program is called that allows the computer to automatically restart.

Block 9 commit failure works as follows.

When a signal is output from the output of counter 7, the one-shot 14 starts up and the counter 15 is triggered once. If the restart was successful, then there was a failure and there was no secondary signal from the output of counter 7.

Then the one-shot 14 is triggered, and from its output the signal of setting to zero goes to the second input of counter 15 and resets it. Thus, at the output of block 9 latch 191I failure does not issue a signal. In the event of a sustained failure, a secondary signal is issued from the output of counter 7, and this signal causes the counter 15 to re-activate. At the first and second inputs of the element 17, single signals appear, and at the output of the element 17 there is an alarm.

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Editor E. Kopcha

Compiled by I.Safronova

Tehred O. Vashchishin Proofreader L. Pilipenko.

8536/51 Tefazh 709 Subscription VNIIPI USSR State Committee for Inventions and Discoveries 4/5, Moscow, Zh-35, Raushsk nab. 4/5

Filial PPP Patent, g, Uzhgorod, st. Project, 4

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Claims (1)

A device for restarting a computer containing a trigger, an encoder, a micro-command address register, a micro-command memory block, a decoder and a driver of control signals, the first input of the encoder being connected to the direct output of the trigger, the second input of the encoder being the input of the device error detection signal, the encoder output connected to the register input addresses of microcommands, the output of which is connected to the address input of the memory block of microcommands, the output of which is connected to the input of a decoder, the group of outputs of which is a group of control odov device, the first output of the decoder is connected to the zero input of the flip-flop, the input unit is an input device which interrupts, characterized in that, in order to increase the speed of computer restart, the device comprises a ge- / a pulserator, a counter, a block for fixing a failure, and a driver of control signals contains a one-shot, a delay element, a trigger, an OR element, the output of a one-shot connected to the first input of the OR element, the output of which is connected to the third input of the encoder, the output of the delay element is connected to the zero input of the trigger , a single trigger input, a delay element input and a single-vibrator input are combined and connected to the output of the device counter, a direct trigger output is connected to the counter signal enable input, the output is ele The OR gate is connected to the third input of the device encoder, the second input of the OR element is the input of the device zero level signal, the failure lock block contains a single vibrator, counter, element NOT and the AND element, and the output of the single vibrator is connected to the counter reset input, the outputs of the first and second bits of which are connected respectively, with the input of the element NOT and the first input of the element AND, the second input of which is connected to the output of the element NOT, the output of the element AND is the signal output of the device, the input of the one-shot and the counting input of the counter and are combined and connected to the output of the counter unit, the pulse generator output is connected to the count input of counter devices, counter reset input device coupled to the first output of the decoder, receiving the enable input counter device is connected to the output of the control signals. ί