SU1196880A1 - Interface for linking message sources with digital computer - Google Patents

Abstract

1. A DEVICE FOR CONNECTING MESSAGE SOURCES WITH A DIGITAL COMPUTING MACHINE, containing a memory block, an address generation unit, a priority code generation unit, an output key, a queue generation unit, a control unit, K queue fixation units, each queue fixing unit containing a register, the priority register, the two OR elements, four keys, and from the second to the K-1 st block of fixing the queue contain two additional keys, with the information input of the memory block and the control input of the address generation unit connected to the information bus of message sources, the first input of the control unit is connected to the control bus of the digital computer, the first information output of the memory unit is connected to the information bus of the digital computer, the second information output of the memory unit is connected to the information input of the address generation unit, the information the output of which is connected to the address input of the memory unit and the information inputs of the first keys K of the queue latching units, the output of the connection queue shaping unit It is connected with the second input of the control unit, the output of which is connected to the control input of the output key, the output of which is connected to the control input of the memory unit, the first group of outputs of the control unit is connected to the control inputs of the first and second keys in the corresponding K queue latching blocks, the second group of outputs of the control unit is connected to the information inputs of the third and fourth keys in the corresponding queue latching blocks corresponding to the first i RK-1, (L, in each queue latching block, the first and the second inputs are The first OR element is connected to the outputs of the first and third keys, respectively, the first and second inputs of the second OR element are connected to the outputs of the first and third keys, respectively, the first and second inputs of the second OR element are connected to the outputs 00 of the second and fourth keys, respectively, the outputs the first and second elements OR are connected to the inputs of the register of the attribute and the priority register, respectively, the outputs of the priority registers of all the queue-fixing blocks are connected to the corresponding information inputs t bl Single forming queue, wherein the queue tag registers vkody fixing blocks of the first to K-J-2 are connected to the data inputs of said fifth key locks b fixation queue second through K-th, respectively, outputs of feature registers in units of fixation

Description

the second to Kth queues are connected to the control inputs of the third keys in the first to K-1 queue fixation blocks, respectively; the outputs of the priority registers of the first to K-2 queue fixation blocks are connected to the information inputs of the sixth keys block fixing the queue, the outputs of the priority register in the second-to-th queue latching blocks are connected to the control inputs., the fourth keys to the first to K-1 queue latching blocks, respectively, the output of the sign register of the K-th queue fixing block with information the output of the output key, and the output of the register of the sign of the K-1 th queue latch block is connected to the information input of the third key of the K th queuing block; the output of the priority register K-1 of the queue latch block is connected to the information input of the fourth key of the K th the block of fixing the queue, wherein in each block of fixing the queue from the second to the K-1th outputs of the fifth and sixth keys are connected to the third inputs of the first and second elements OR, respectively, characterized in that, in order to extend the functionality It is possible to change the priority of an incoming message depending on the queue state, a queue state analysis block, a queue recovery block, a group of OR elements are entered into it, and the message code register and the third OR key are entered into each queue block; The fifth and sixth keys are entered into the queue fixation block, the seventh, eighth, and ten keys are entered into the second to K-1 queue fixation blocks: the first input of the queue state analyzer is connected to the information source bus The first output of the queuing state analysis block is connected to the information inputs of the fifth keys in the first and Kth blocks of the queue fixer and the seventh keys in the second to K-1 queue fixation blocks, the outputs of the message code registers. To the queue fixation blocks with the group of inputs of the block of the state of the queue analysis, the second output of which is with the information input of the priority code generation unit, the information output of which is connected to the second input of the queue state analysis block, the third output of which is connected with the information by the moves of the second keys To the queue latching units and to the third input of the control unit, the third group of outputs of which are connected to the first inputs of the OR elements of the group, the group of outputs of which are connected to the control inputs of the fifth, sixth and eighth keys in the blocks of queue fixation from second to K -1-fi and with the control inputs of the third, fourth, and sixth keys in the Km block for fixing the queue, a quarter output of the block for analyzing the state of the queue is connected to the trigger input of the restoring queue block, the group of information inputs of which connected to the corresponding outputs from the first to K-1 of the first group of outputs of the control unit, the group of outputs of the queue recovery block is connected to the second inputs of the OR elements of the group, the inputs from the code registers of the block messages of the queue from the third to K are connected to the control, the inputs of the ninth keys of the message lock block from the second to the K-1, respectively, the output of the message code register of the second block f) And the queue queue is connected to the control input of the sixth key of the first queue lock block, the outputs of registers and the messages of the first-to-K-2 queue fixation blocks are connected to the information inputs of the eighth keys of the second-to-K-1 fixation queue blocks, respectively, the output of the message code register K-1 of the queue fixing block is connected to the information input of the sixth key K-th block fixing the queue, while in all blocks of fixing the queue, the output of the third element OR is connected to the inputs of the message code register, in the blocks of fixing the queue from the second to the K-1st information input of the ninth key is connected to the information input of the third key , the control input of the seventh key is connected to the control input of the first key, the outputs of the seventh, eighth, and ninth keys are connected to the first, second and third inputs of the Tpetbero element OR, respectively, in the first IR-block of the queue fixing control input the key is connected to the control input of the first key, the outputs of the fifth and sixth keys.

whose first and second inputs of the third element OR, respectively, in the first queue-fixing unit, the information input of the sixth key is connected to the information input of the third key, and the control unit contains a clock generator, a reference node, a decoder, two elements AND, two an OR element, two triggers, two clock distribution nodes, a group of AND elements and a group of BANKS, the single input of the first trigger being the first input of the control unit and connected to its output, the first The output input of the comparison node is the second input of the control unit, the second information input of the comparison node is the third input of the control unit, the outputs of the AND elements of the group are connected to the input group of the first OR element, and form the first group of outputs of the control unit; the outputs of the BANNER groups form the second group of outputs control unit, the group of outputs of the first clock distribution unit forms the third group of outputs of the control unit, while in the control unit the output of the first element OR is connected with the zero input of the second trigger, the reset input of the second clock distribution node, and the control input of the comparison node, the output of which is connected to the input of the decoder, the group whose outputs are connected to the first inputs of the AND group elements and the BANNER elements of the group and the input group of the second OR element, the output of which is connected to the single input of the second trigger, the output of which is connected to the first input of the first element I, the second input of which is connected to the output of the clock pulse generator and the first input of the second el ement And; the output of which is connected to the input. starting the first clock distribution node, the last output of which is connected to the zero input of the first trigger, the output of which is connected to the second input of the second element, And the output of the first element And is connected to the start input of the second clock distribution node, whose output group is connected to the second inputs of the AND elements groups and elements of the banned group.

2. The device according to claim 1, wherein the queue state analysis block contains a buffer register, an adder, a memory of the priority changes, a comparison node, a critical memory, the information input of the buffer register being the first input of the block, a group of information inputs the comparison node forms a group of block inputs, the information output of the buffer register is connected to the information input of the priority changes memory and is the first and second outputs of the block, the first input of the adder is the second input of the block, and the output d - the third one: block stroke, the first output of the comparison node is the fourth output of the block, while in the block of the state queue analysis analysis, the memory output of critical situations is connected to the information input of the comparison node, the second output of which is connected to the address input of the priority changes memory whose output is connected to the second input of the summator,

3. The device according to claim 1, characterized in that the queue recovery block contains a trigger, a buffer register, a generator

clock pulses, clock distribution node, AND element, OR element, AND group of elements, BANGE group of elements, the single trigger input is the starting INPUT of the block, the information input group of the buffer register forms the group of information inputs of the block, the outputs of the AND elements of the group form the group of outputs of the block, while in the block of restoring the queue the group of outputs of the buffer register is connected to the first inputs of the elements AND of the group and the elements of the BANGE group whose outputs are connected to the group of inputs OR, whose output is connected to the reset input of the clock distribution node and the zero trigger input, the output of which is connected to the first input of the AND element, the second input of which is connected to the output of the clock generator, and the output to the start input of the clock distribution node which is connected to the second inputs of the elements And the group and the elements of the banned group. The invention relates to automation and computer technology, in particular, devices for interfacing message sources with control computers, and can be used in control systems for aircraft with increased autonomy. The purpose of the invention is to expand the functionality due to the possibility of changing the priority of the incoming message depending on the queue state. FIG. 1 shows a block diagram of the device; in fig. 2. The block diagram of the control unit; in fig. 3 is a block diagram of a priority code generation unit; FIG. A is a block diagram of a queue recovery unit; in fig. 5 is a block diagram of an address generation unit; in fig. 6 is a block diagram of a queue status analysis block; in fig. 7 is a block diagram of a queuing unit. A device for interfacing message sources with a digital computer contains (Fig. 1) memory block 1, address generation block 2, priority code generating block 3, output switch 4, queue shaping block 5, control block 6, K blocks 7- 10 latch queues, a queue status analysis block 11, a queue recovery block 12, an OR 13 group of elements, a priority register, a characteristic register 15, a message code register 16, the first, second and third elements OR 17 are contained in each queue latch block. - 19, in queue fixation blocks with torogo K-1-th contained nine keys 20, 28 in the first and the K-th block fixation och mong contained six keys 29 - 34 of FIG. Figure 1 also indicates information input 35 from sources of communications, control input 36 from a digital computer, information output 37 on a digital computer. The control unit 6 comprises (FIG. 2 a comparison node 38, a decoder 39, a first element OR 40, a second element OR 41, first and second elements AND 42 and 43, first and second triggers 44 and 45, a second pulse distribution node 46, the first pulse distribution node 47, clock pulse generator 48, AND 49 group of elements, BAN 50 50 element block. The priority code generation unit 3 contains (FIG. 3) a possible message memory 51, a comparison node 52, a priority memory 53. contains (Fig. 4) the trigger 54, the element And 55, the generator 56 clock them pulses, node 57 of the distribution of clock pulses, a group of elements BANCH 58, a group of elements AND 59, an element SH 60, a buffer register 61. The address generation unit 2 contains (FIG. 5) a pulse shaper 62, a switch 63, a decoder 64, an address memory 65 cells, register 66. The queue status analysis block 11 contains (FIG. 6) a buffer register 67, an adder 68, a priority change memory 69, a comparison node 70, a critical memory 71. The queuing unit 5 contains (FIG. 7) a group of registers 72, a switch 73. The device operates as follows. For the device is characterized by two modes of operation. The first-mode occurs when a message arrives at device input 35 from message sources. This mode consists in setting the sign of the message that has clicked on the queue position in accordance with the state of the queue at the time of its arrival. The status of a queue is determined by the number of messages queued, i.e. the number of occupied registers is 15 blocks 7–10, the priorities and content of messages queuing. Composing the incoming message to the queue assumes a shift towards the last position in the queue (reverse shift) of all message attributes that have priorities less than that of the received message, and recording the sign of the incoming message to the free space (in the corresponding register 13 of blocks 7-10). After this, the queue state analysis block 11 analyzes the current situation in the queue that has developed after the new message has been queued. When a critical situation occurs, the queue state analysis block 11 sends a signal to the queue recovery unit 12, which restores the original state of the queue (the state before the arrival of the new message), changes the priority of the incoming message and produces

3 1

Record a sign of this message to a new place in the queue.

The second mode takes place when the service signal arrives at input 36. According to this signal (end of service of the previous message), control unit 6 ablates the message indication sample signal at the K-th position of the queue in register 15 of the block .10 and signals at the third a group of inputs that sequentially overwrite the characteristics of messages from the register 15 of the next block to the register 15 of the next block (direct queue shift).

Consider the operation of the device in the first mode. The message is fed to the input device 35. The address generation unit 2 generates. code., the address of the free cell of memory 1 as follows.

By its second information output, memory block 1 provides information on free cells to address generation unit 2. This information is decoded by the decoder 64,

.and under its influence the switch 63 switches the impulse arriving

..former 62 pulse (when a message arrives at the input 35 of the device) at one of its outputs. In this case, the code of the address of the free cell is selected from the memory of the addresses of the cells, which is written to the register and fed to the block 1 of the memory. A message is recorded at this address in memory block 1. At the same time, the message is written to buffer register 67 and JB receives the priority code generation unit 3 at the comparison node 52. At comparison node 52, this message is compared with all possible messages that are stored in memory 51 of possible messages. According to the result of this comparison, one of the priority values is selected from the priority memory 53, which is assigned to this message. The assigned priority then goes to adder 68, since in this case no information arrives at the second input of adder 68, the priority does not change. Code . the priority is then sent to control unit 6, where it is compared in comparison node 38 with information received from queue generation unit 5. The switch 73 of the block 5 forming a queue on request

Comparison 38 registers 72 successively. Registers 72 store codes, the first bits of which, constant codes, represent

5 are the codes of the corresponding positions of the queue, and the remaining bits are the priority codes of the messages placed at these positions in the queue. As a result of the comparison, in node 38 of the comparison of priorities, the decoder 39 receives the code of the position of the queue, which has the lowest of priorities but less assigned to this message. At one output of the decoder 39, a positive potential appears. Along the front of this potential, the trigger 45 is set to one. This also opens the element AND 49 and all the elements BANKS50,

20 except for one corresponding to the given element AND 49. The high potential of the trigger 45 opens the element And 42, and the pulses. From the generator 48 clock pulses begin to flow on

25 input of the second node 46 distribution

clock pulses. After that, so. These pulses begin to sequentially arrive at the second group of outputs of control block 6, thereby realizing sequential rewriting of message signs with priorities lower than the incoming message from the register 15 of one block to register 15 of the previous block through the keys 29 or 22 blocks 7-9.

5 At the same time, a priority census is made from the priority register of one block into the priority block 14 of the previous block via keys 23 or 32 blocks 7-9 and the message code is copied from register1 1 b of one block to register 16 of the previous block of the block via key 28 or 34 Blocks 7 to 9. After all information about the messages with priorities is less than the priority of the received message is rewritten, the pulse from the second clock distribution node 46 passes through the open element I 49 to

50 is one of the outputs of the control unit 6. This output corresponds to the position at which the incoming message is recorded. In this case, the sign of the received message is recorded in register 15 of the sign from register 66 through the keys 20 or 31 of the corresponding block, the content code of the message is sent to register 16 from the buffer register 67

through the keys 26 or 33 of the corresponding block, and the priority code into the register 14 from the adder 68 through the keys 21 or 30. In addition, this pulse through the element OR 40 resets the comparison node 38 and converts the trigger 45 to the zero state. for pulses element AND 42, this pulse also sets in the initial state the second node 46 of the distribution of clock pulses. At this stage of pre-setting

the message in the queue ends. I

After that, the state analysis and queue analysis unit 11 automatically performs a queue status analysis. The state of the queue may be normal and critical. Critical is the state of a queue in which the order of dependent messages from one another is broken, i.e. intervention of the queue status analyzing unit 11 is required to redefine the priority of the incoming message. This is implemented automatically by means of a memory of 71 critical situations in which all critical situations are stored with a known volume of messages. The presence of a critical situation is detected by the comparison node 70, which in this case generates a critical situation code on the second output, and a signal on the queue recovery unit 12 on the first output. This signal triggers the trigger .54, thus opening the element. And 55. The pulses of the generator 56 clock pulses begin to appear on the node 57 of the distribution of clock pulses. In this case, the buffer register 61 stores information about the position number in the queue in which the incoming message has been delivered. A high level will be only on one of its. Exits. In this case, respectively, only one element And 59 and all of the elements of the prohibition 58, except for one corresponding to this position in the queue, are open. Clock pulses from the outputs of the clock pulse distribution node 57 through elements Z. Pret 58 carry out a consecutive rewrite of the codes of the signs of messages with priorities lower than the priority of the received message from register 15 of one block 7-9 in register 15 of the subsequent block 8,9,10 through the corresponding keys 24 or 31

In this case, simultaneous rewriting of priority codes from register 14 of one block 7–9 to register 14 of a subsequent block 8 is performed. - 10 through the corresponding keys 25 or 32 and message codes from register 1.6 of one block 7–9 to register 16 of a subsequent block 8 - 10 through the corresponding keys 27 or 34. After all information about the messages, whose priority is lower than the priority of the received message, is recorded, the pulse of the clock distribution unit 57 through the open element And 59 and the element WIT 60 sets the source state 57 distribution of clock pulses and to the zero state trigger 54, the same element And 55 is closed for clock pulses. Circuit state restored. Thereafter, the critical code from the comparison node 70 enters the priority change memory 69, at the output of which a priority changing code is selected for this critical situation and this message. This code enters the adder 68, and the changed priority of the message from the adder 68 again triggers the control block 6 to place the incoming message with the new priority in the queue.

Consider the function of the device in the second mode.

In this case, the input 36 is supplied with a signal (the end of the service of the predictive message), which is fed to the output of the control unit 6. In this case, the sign (address) of the message, standing on. The kth position in register 15 of block .10 is sent via output switch 4 to memory block 1, from which the message is selected at output 37 of the device. At the same time, this signal sets the trigger 44 to one state, opens element 43. After that, the pulse generator 48 clock pulses begin to flow to the first clock pulse distribution node 47, which begins to generate successive signals that carry out a sequential rewriting of the codes of message signs from the register 15 of one block 7 - 9 in the register 15 of the subsequent block 8-10 through the corresponding key 24 or 31. In addition. the simultaneous rewriting of priority codes from register 14 of one block 7–9 to the register of subsequent block 8–10 through a corresponding key 25 or 32 and message codes from register 16 of one block 7–9 to register 16 of subsequent block 8-10 through the corresponding The key is 27 or 34. The last of the pulses of the first node 47 of the distribution of clock pulses transfers the trigger 44 to the zero state by closing the pulse to the input of the first node .47 of the distribution of clock pulses. Therefore, 08 is a forward queue shift. . . The invention allows to quickly solve management issues. For example, in the case of controlling several subsystems of an object using a single digital computer, the quality of management is improved by taking into account operational changes of important parameters to create the necessary correction of control actions outputted to subsystems that are at worst from the point of view of the quality of management. This increases the stability and autonomy of control of the object.

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Claims (3)

1. DEVICE FOR PAIRING SOURCES OF MESSAGES WITH A DIGITAL COMPUTER MACHINE, containing a memory unit, an address generation unit. CA, priority code generation unit, output key, queuing unit, control unit, K queue fixation blocks, each queue fixation block contains a sign register, priority register, two OR elements, four keys, and second to K-1 queue fixation blocks contain an additional two keys, while the information input of the memory block and the control input the address generation unit is connected to the information bus of the message sources, the first input of the control unit is connected to the control bus of the digital computer, the first information output of the memory unit is connected to the information bus of the digital computer of the machine, the second information output of the memory unit is connected to the information input of the address generation unit, the information output of which is connected to the address input of the memory unit and the information inputs of the first keys K of the queue fixation blocks, the output of the queuing unit is connected to the second input of the control unit, the output of which is connected to the control input of the output key, the output of which is connected to the control input of the memory unit, the first group of outputs of the control unit is connected to the control inputs of the first and second x keys in the corresponding K blocks of fixing the queue, the second group of outputs of the control unit is connected to the information inputs of the third and fourth keys in the corresponding from the first pr K-1 block of fixing the queue, while in each block of fixing the queue the first and second inputs of the first element OR connected to the outputs of the first and third keys, respectively, the first and second inputs of the second element OR connected to the outputs of the first and third keys, respectively, the first and second inputs of the second element OR connected to the outputs of the second and the fourth key, respectively, the outputs of the first and second OR elements are connected to the inputs of the attribute register and the priority register, respectively, the outputs of the priority registers of all queuing blocks are connected to the corresponding information inputs of the queuing block, and the outputs of the sign registers of the queuing blocks from the first to K- 2-nd are connected to the information inputs of the fifth keys of the blocks of fixing the queue from the second to the K-th, respectively, the outputs of the attribute registers in the blocks of the fixation SU. „, 1196880 On the K-th are connected to the control inputs of the third keys in the queue lock blocks from the first to the K-1st, respectively, the outputs of the priority registers of the queue lock blocks from the first to the K-2 are connected to the information inputs of the sixth keys of the queue lock blocks, the outputs priority registers in the second-by-Kth queue fixing blocks are connected to the control inputs. the fourth keys in the first-by-K-1st queue fixing blocks, respectively, the output of the sign register of the Kth queue fixing block is connected to the information input of the output lucha, and the output of the attribute register of the K-1 block of the queue is connected to the information input of the third key of the K-th block of the queue, the output of the priority register of the K-1 block of the queue is connected to the information input of the fourth key of the K-block of the queue Moreover, in each block of fixing the queue from the second to the K-1, the outputs of the fifth and sixth keys are connected to the third inputs of the first and second elements OR, respectively, characterized in that, in order to expand the functionality due to the possibility of changing ioriteta incoming message ¹ depending on the state of the queue, it introduced analysis unit queue status block queue recovery element group OR, wherein in each block queue fixation introduced Register message code, and a third OR gate, the first K ~ nd stage fixing unit the fifth and sixth keys are entered, the seventh, eighth, ninth keys are entered into the second and K-1 queue lock blocks, the first input of the queue status analysis unit being connected to the information bus of the message sources, the first output of the analysis unit The queue states are connected to the information inputs of the fifth keys in the first and Kth queue fixing blocks and the seventh keys in the second and K-1 queue fixing blocks, the outputs of the message code registers of the K queuing blocks are connected to the group of inputs of the queue state analysis block, the second output of which is with the information input of the priority code generation unit, the information output of which is connected to the second input of the queue state analysis unit, the third output of which is connected to the information inputs of the second keys K of fixed blocks of the queue and with the third input of the control unit, the third group of outputs of which is connected to the first inputs of the OR elements of the group, the group of outputs of which is connected to the control inputs of the fifth, sixth and eighth keys in the blocks of fixing the queue from the second to K-1 'and the control inputs of the third, fourth and sixth keys in the Kth block of fixing the queue, the fourth output of the queue state analysis unit is connected to the triggering input of the queue recovery unit, the group of information inputs of which are connected to the corresponding output from the first to the K-1 from the first group of outputs of the control unit, the group of outputs of the queue recovery unit is connected to the second inputs of the OR elements of the group, the outputs of the message code registers of the blocks of hold of the queue from the third to the K-th are connected to the 'control, inputs of the ninth keys message fixation blocks from second to K-1, respectively, the output of the message code register of the second Queue lock block is connected to the control input of the sixth key of the first queue lock block, the outputs of the message code register registers of the queue lock blocks from the first the first in K-2nd are connected to the information inputs of the eighth keys of the queue fixation blocks from the second to the K-1st, respectively, the output of the message code register of the K-1-th block of the queue is connected to the information input of the sixth key of the K-th block of fixation ^ di, in this case, in all blocks of the queue fixing, the output of the third OR element is connected to the inputs of the message code register, in the blocks of the queuing from the second to K-1, the ninth key information input is connected to the third key information input, the seventh key control input is connected to up with the input of the first key, the outputs of the seventh, eighth and ninth keys are connected to the first, second and third inputs of the third OR element, respectively, in the first and Kth blocks of the queue fixation, the control input of the fifth key is connected to the control input of the first key, the outputs of the fifth and sixth the keys are connected to the first and second inputs of the third OR element, respectively, in the first block fixing the queue, the information input of the sixth key is connected to the information input of the third key, while the control unit contains a generator actuation pulses i comparison node, decoder, two AND elements, two OR elements, two triggers, two clock distribution nodes, a group of AND elements and a group of FORBID elements, the single input of the first trigger being the first input of the control unit and connected to its output, the first information the input of the comparison node is the second input of the control unit, the second information input of the comparison node is the third input of the control unit, the outputs of the AND elements of the group are connected to the group of inputs of the first OR element and form the first group of outputs of the control unit *, the outputs of the elements of the PROHIBITED group form the second group of outputs of the control unit, the group of outputs of the first distribution node of the clock pulses forms the third group of outputs of the control unit, while in the control unit the output of the first OR element is connected to the zero input of the second trigger, the reset input of the second clock distribution node and the control input of the comparison node, the output of which is connected to the input. a decoder house, a group whose outputs are connected to the first inputs of AND elements of the group and elements of the FORBID group and a group of inputs of the second OR element, whose output is connected to the unit input of the second trigger, the output of which is connected to the first input of the first AND element, the second input of which is connected to the output clock generator and the first input of the second element And ', the output of which is connected to the start input of the first node of the distribution of clock pulses, the last output of which is connected to the zero input of the first trigger, output One of which is connected to the second input of the second AND element, the output of the first And element is connected to the start input of the second clock distribution node, the group of outputs of which is connected to the second inputs of the AND elements of the group and the elements of the FORBID group. 2. The device according to p. 1, characterized in that the queue state analysis unit contains a buffer register, an adder, a memory of priority changes, a comparison node, a memory of critical situations, the information input of the buffer register being the first input: the block house, a group of information inputs of the node comparison forms a group of inputs of the block, the information output of the buffer register is connected to the information input of the memory of priority changes and is the first and second outputs of the block, the first input of the adder is the second input of the block, and the output - the third output of the block, the first output of the comparison node is the fourth output of the block, while in the analysis block of the queue state the critical situation memory output is connected to the information input of the comparison node, the second output of which is connected to the address input of the priority change memory, the output of which is connected by the second input of the adder 3. The device according to claim 1, characterized in that the queue recovery unit comprises a trigger, a buffer register, a clock • generator, a clock distribution node, an AND element, an OR element, an AND group of elements, an INHIBIT element group, and the trigger has a single input by the starting input of the block, the group of information inputs of the buffer register forms a group of information inputs of the block, the outputs of the elements AND the groups form a group of outputs of the block, while in the recovery block of the queue the group of outputs of the buffer register is connected is not with the first inputs of AND elements of the group and elements of the FORBID group, the outputs of which are connected to the group of inputs of the OR element, the output of which is connected to the reset input of the clock distribution node and the zero input of the trigger, the output of which is connected to the first input of the AND element, the second input of which is connected to the output of the clock generator, and the output is with the start input of the clock distribution node, the group of outputs of which is connected to the second inputs of the AND elements of the group and the elements of the FORBID group.