SU1195393A1 - Memory - Google Patents

Description

The invention relates to computing and can be used to create high-speed systems with increased reliability.

The aim of the invention is to simplify and improve the speed of the device.

Fig, 1 shows a functional diagram of the device; in fig. 2 - functional diagram of one of its blocks; in fig. 3 - timing diagrams explaining the operation of the device.

The device (Fig. 1) contains a switch 1c inputs 2 control input-15 house 3, inputs 4 and outputs 5, the encoder 6, the drive 7 with outputs 8, the first block 9 error correction, the first block 10 calculating the sign of error, the second block 11 error correction 20 with inputs 12 and 13, the first 14 and second 15 decoders, block 16 from the input "MI 17 and 18 and outputs 19-21, register

22, the second calculation block 23 recognizes. . -

ka mistakes. FIG. 1 designates the address- 25 inputs of the device 24 and one of the outputs 25 of the register 22. The device also includes a control block 26 with an output 27 and an information output block 28 with the outputs 29. 30

Block 16 (Fig. 2) Contains the first element OR 30 with the output 31, the convolution unit 32 modulo two with the output 33, the first to the third elements AND 34-36 and the second element OR 37 with the input 38.

FIG. The information signals at inputs 2 and the signals at inputs 3 and 24 in the recording mode are shown; in fig. FIG. 3 K - signals at inputs 3 and 24, read information signals at outputs 8, signals at inputs 17, signals at outputs 19 and 20 and information signals at outputs 29 in read mode.

The device works as follows.

In the write cycle, the input information about the inputs 2 (Fig. 1) is placed in the switch 1, on the basis of which the encoder 6 generates check binary characters. Thus, the generated code word is written into the drive 7 at the address set at the inputs 24.

In the read cycle, the read word 55 from -8 of drive 7 enters blocks 9 and 10. In the absence of errors, the error sign is zero, on

input 18 is a single signal indicating that register 22 is empty, i.e. in the interrogated memory elements (EP) and previously there were no faults. Read information symbols pass through blocks 9 and 11 to block 28 and further to the outputs 29 of the device. When the first error appears, its non-zero sign is generated by block 10 and has an odd weight. The calculated error symptom passes through block 23 without changes, since at the output 25 of the register 22, only zero binary signals are set. Further, in the decoder 14, the sign of the error is decoded, i.e. the location of the erroneous discharge is set, and in block 9 the error is corrected. The code word, in which there are no errors, from the output of block 9 through input 4 enters the switch 1, and the information bits of this word are fed to the outputs 29 of the device. 20 '

(Fig. 3) single signals are generated that allow writing the corrected code word from switch 1 to the polled drive ES 7> and the error sign from the outputs of block 10 to the register 22. If the detected error occurs due to the failure of the EA, then the correct the bit changes the state of this element; in the next cycle, there will be no error in the word from the same EA. The output of information to the device outputs 29 is the same as in the case when there were no errors at all. 0 however ^; a single signal at the output of element 38 of the AND 34 (Fig. 2}, acting through the element OR 37 at the output of 20, allows the register 22 to be reset to zero, in which information about the previous failure has been recorded.

If the failure of the ES occurred earlier, the state of the corresponding ES of the drive 7 and the bits of the register 22 does not change, since zero signals are set at the outputs 19 and 20.

If, during subsequent calls to the EA, a zero sign of an even weight error is detected in the read cycle, i.e. single signals at outputs 31 and 33, this means that two errors were detected in the read word, which occurred in the interval between the last two cycles of H95393

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lamy. In this case, a single signal at the output 21 gates the block 28 and thereby prohibits the issuance of information to the outputs 29 of the device. In addition, the interrupt signal reports ς

processor (not shown) about the appearance of a double error. If one of the faults in the ES (failure or failure) occurred in the previous cycles, as evidenced by the zero signal on the 0 input 18, then the outputs 19-21 also have zero signals, i.e. there is no change in the state of the polled VC and cells of register 22. The sign of a double error from the output of block 10, sum-15, is read in block 23 with a sign of a single error that occurred earlier, which is fed to the inputs of block 23 from outputs 25 of register 22. At one of the outputs of the decoder 14, a 20 signal appears, which in block 9 corrects the error , which occurred later, and in block 11, the error that had arisen earlier is corrected, thus, the word 25 arrives at the device outputs 29 'without errors.

A single signal at the output of the 31 element OR 30 appears in the case

if the read word contains errors (one or several bits were read incorrectly), i.e. error sign is nonzero. A single signal at output 33 of block 32 indicates that an odd number of errors have occurred. A single signal at the input 18 appears if there were no errors in the read word in the previous reading cycle, i.e. when the register 22 is empty. Single signals at outputs 19 and 21 are set _; accordingly, when one error is detected in a word and when two errors appear simultaneously in the last cycle and one in the previous one. In the presence of a single signal at the output 20 in the register 22 is recorded information received at the inputs 17.

In the proposed device, the number of errors is wrong, as in the well-known, however, its speed in read mode is approximately 30-40 I higher than the speed of the known, taking into account that the same time is required for recording and reading information.

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Claims (1)

A STORAGE DEVICE containing an accumulator, an encoder, an error correction block, an error sign calculating block, a decoder, an information output block, a register, a control block, the first and second OR elements, a convolution block modulo two, the AND elements and a switch, one of whose outputs are the information inputs of the device, and the outputs are connected to one of the information inputs of the drive and the inputs of the encoder, the outputs of which are connected to other information inputs of the drive, the control input of which is connected to the output of the unit pack The outputs and outputs are connected to one of the inputs of the first error correction block and the inputs of the first block for calculating the error sign, the outputs of which are connected to the inputs of the first OR element, the convolution block inputs modulo two, the information inputs of the register with one of the inputs of the second error sign calculator, the outputs of which are connected to the inputs of the first decoder, the outputs of which are connected to other inputs of the first error correction block, the outputs of which are connected to other inputs of the switch and one of the inputs of the second correction block Ccci errors, the outputs of which are connected to the inputs of the information output unit, and the other inputs are connected to the outputs of the second decoder, the inputs of which and other inputs of the second unit for calculating the error symptom are connected to one of the outputs of the register, the other output of which is connected to the first inputs of the elements And, from the first on the third, the second inputs which are connected to the output of the first element OR, the third inputs of the second and third elements AND are connected to the output of the convolution unit modulo two, and the output of the third element And is the control output us Triplets, whose address inputs are the address inputs of the switch and storage device, characterized in that, in order to simplify and improve the device performance, the inputs of the second element OR are connected to the outputs of the first and second elements AND, and the output is connected to the control: register input, output of the second element And connected to one of the inputs of the control unit, and the output of the third element I - to the first control input of the information output unit, the second control input of which, the other input of the control unit and the control input switch pa is the control input of the device. <2 with SL WITH WITH with 5> 1 1195393 2