SU1180938A1 - Device for reading graphic information - Google Patents

Description

The invention relates to automation and computing and can be used in information-computing systems and in computer-aided design, control, training as means of reading graphic information for inputting it into a computer, transferring it to a display device or to a storage system. YU

The purpose of the invention is to improve the accuracy and speed of the device.

The drawing shows the block diagram of the device.

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The device contains the first generator of pulses, the first element OR 2, the first trigger 3, the first element AND 4, the second element OR 5, the switch 6, the second trigger 7, the second element AND 8, the first delay element 20 9, the third element OR 10, the first group of elements AND 11 and 12, the second group of elements AND 13 and 14, the third control trigger 15, the fourth element OR 16, the first counter is 25 lines 17, the second counter is 18 lines, the first counter is 19 frames, the second element is 20 delays, the second counter 21 frames, the fifth element OR 22, the third element 23 AND, the fourth 30 element 24 delays, ne the second driver 25 signals, trigger 26 blanking, the third delay element 27, the second driver 28 signals, the fourth trigger 29, neck-35 that element OR 30, the seventh element OR 31, the indicator 32, containing blocks 33 and 34 of the beam deflection along the X coordinates and Υ and CRT 35 with a deflecting system, the third generator 36 signals, the fourth driver 37 signals, the first selector 38, the fourth element And 39, the fifth element And 40, the second generator 41 pulses, the ninth element 45 OR 42, the fifth element 43 delay , the eighth element OR 44, the first register 45, the fifth trigger 46, the tenth element OR 47, the first output 48 of the device, the eighth element 49 delay, the eleventh delay element 50, the sixth element AND 51, the block

52 analog-to-digital conversion, including the third generator

53 pulses, second selector 54, 55

brightness forming counter 55, fifth driver 56 signals, Digital-to-analog converter 57,

the seventh element And 58, the element 59 comparison, the sixth trigger 60, the sixth element 61 delay, the seventh element 62 delay, the eleventh element OR 63, the distributor 64 pulses, the seventh trigger 65, the ninth element 66 delay, the counter 67 cycles, the tenth element 68 delay a decoder 69, a second register 70, a second device output 71, a third storage register 72, a first 73, a second 74, and a third 75 device inputs and a third device output 76.

The device works as follows.

The enable signal, which appeared at the input 73 of the device, sets the trigger 3 to the state "1". The pulses from the generator 1 are fed to the input of the element AND 4. In the initial state, the triggers 7, 15, 29, 46,

60 are in "o". The pulses from the element And 4 are fed to the input of the counter 17 lines, to the installation in the "0" of the counter 18 lines and the counter 19 frames. The increasing values of the counter codes 17 and counter 21 enter the blocks 33 and 34, and the beam changes its position on the screen of the CRT 35 of the indicator 32 by the value of the first slot element along the OX coordinate. In this case, the pulse from the generator 1 enters the element OR 44, from the output of which the pulse through the driver 28 signals and the element OR 22 sets the trigger 26 to "1".

As a result, a CRT 35 beam is quenched via the signal shaper 25. The pulse from the OR 44 element is delayed through the 24 element and the OR 30 element sets the trigger 26 to "0". The CRT 35 beam is again illuminated. In this way, the beam is extinguished during transients in the device during the passage of signals. Increasing codes from the outputs of counters Ί7 and 21 are fed to the inputs of register 45.

If there is a video signal at the input 75 of the device equal to ”1", it is fed to the element 59 of the block 52 and the driver 36 of the signals from the output of which it is fed to the counter 55 and the driver 28 of the signals. The signal from the driver 36 records the contents of the counters

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17 and 21 to register 45, from the output of which the current values of the X and Y coordinates are fed to the first output 48 of the device.

The pulses from the generator 53 are fed to the counter 55, and the constantly increasing code from the output of the counter 55 is fed to the first inputs of the element And 58 and to the inputs of the digital-to-analog converter 57, from the output of which the signal is fed to the second input of the element 59 comparison. When the amplitude of the voltage of the video signal and the amplitude of the voltage from the digital-to-analog converter 57 are equal, a signal is generated from the output of the element 59, which is fed to the driver 56 of the signals; selector 54 selection of the leading edge generates a signal on the leading edge, which is used to write the binary bench of the counter 55 through the element And 58 to the register 70 according to the signal from the element OR 44 through the element 49 of the delay. Parallel binary code brightness from the register 70 enters the decoder 69.

When the amplitude of the video signal voltage is equal to a single value, the signal from the first output of the decoder 69 through the element AND 40, the element OR 31 and the element OR 47 sets trigger state 7 and trigger 46 to the state "0", through element OR 10 - trigger 15, through the OR element 63 and the delay element 66 is set to ”0” the second register 70 and the counter 55, and the signal from the output of the OR element 44 through the delay element 68 sets the initial state “O” to the register 45 and the register 72.

The zero state of the trigger 29 corresponds to the sign of the output from the 48th device of the X and Y coordinates of large discreteness. When reading information with a large discrete content of the counters 18 and 19 on the third output 76 is issued zero values. The reset to “0" of trigger 29 is performed by a delayed clock pulse from generator 1 through the element OR '44, the element · 24 delay and the element] OR 30.

When the amplitude of the video signal voltage is less than a single (threshold value), from the output 103438 4

The ratora 69 generates a signal that sets trigger 1 to state "1", sets delayed state control to trigger state 1 through control element 62. The signal from the output of trigger 65 goes through the signal conditioner 37 to the indicator-focusing-deflecting system 32 and reduces twice

10 beam diameter of a CRT 35.

The first pulse of the generator 41 enters the distributor 64 pulses, from the first output of which the signal sets to the state

15 ”1" trigger 60 as well as impulse

from generator 41 through element 23, switch 6, element 12 enters (+) the input of counter 18. The increasing value of the coordinate code 20 of the X data from counter 18 enters block 33 to deviate a CRT beam 35 along the OX axis with a smaller discrete diameter the beam on the CRT 35. At the same time, the signal from the counter 18 through the element OR 16 and the element OR 22 sets the trigger 26 to the ”1” state, and the beam is extinguished. The delayed signal from the element 27 of the delay through the element OR 30 is set

30 trigger 26 in "O", and the beam is lit.

If there is a video signal at the input 75 of the device, it enters the comparison element 59 and the driver 35 of the 36 signals, from the output of the latter to the input of the element I 39 and the counter 55 of the block 52. The output from the output of the driver 36 of the signals records the contents of counters 18 and ⁴⁰ 19 72. Block 52 converts the amplitude of the voltage of a video signal into a digital code by the signal from delay element 49 is recorded in register 70. Regardless of 4 $, the amplitude of voltage of the video signal from the second output of the decoder 69, the signal through element 51, element 50 delay sets in

state "1" trigger 29.

50

The first pulse from the generator 41 through the element OR 44, the delay element 24 and the element YLI 30 sets the trigger 29 to ”0”, and the signal 55 from the output of the element OR 44 sets the register 45 and the register 72 to the “O” output.

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The second pulse from the output of the generator 41 is fed to the input element And 23, the eighth element OR 44 and the distributor 64 pulses. The signal from the second output of the distributor 64 pulses through the element OR 5 and the delay element 20 sets the state "1" trigger 15, which leads to the switching of the outputs of the switch 6 to the inputs of the counter 19.

The second pulse from element 23 through switch 6 and element 13 increases the content of counter 19 by one, which leads to deflection of the beam down the axis of the opamp by one sampling, blanking and illumination of the beam.

The video signal from the third input 75 of the device is converted by the block 52 into a digital code, which is recorded in the register 70 by the signal from the OR 44 element via the delay element 49. The video signal through the shaper 36 signals to the first input of the element And 39, to another input of which a signal is sent from the element And 23. From the output of the element And 39 a signal through the element 43 of the delay goes to the first input of the element And 51, to the second input of which a signal from the decoder 69. The signal from the element AND 51 through the delay element 50 sets the state of ^ "trigger 29, which by the signal from the element OR 44 through the delay element 24, the element OR 30 is set to" 0. "The signal from the driver 36 records the contents of counters 18 and 19 in reg A source 72 with output to the device output 76, and a delayed signal from the OR 44 element through the delay element 68 setting the register 72 to the initial state "0".

The third pulse from the generator 41 is fed to the input element And 23, element OR 44 and the distributor 64 pulses. From the third output of the distributor 64, the signal through the element OR 10 sets the trigger 15 to "0", which will switch the outputs of the switch 6 to the counter 18. The third pulse from the generator 41 through the element 23, the switch 6, the element 12 enters the (+) - input counter 18. As a result, the beam on the ELG 35 deviates by one raster element to the right along

axis 0X, is the damping and illumination of the beam.

The video signal from the device input 75 is converted by the block 52 to a digital code, which is written to the register 70 by a signal from the element OR 44. Similarly, as in the second cycle, the 18 and 19 counters are recorded by a signal from the imager 36. To the delayed signal from the element OR 44 through the element 68 delay is set in the "O" register 72, and through the element 24 of the delay and the element OR 30 set to "0" trigger 29.

The fourth pulse from the generator 41 enters the distributor 64 pulses, from the fourth output of which the signal through the delay element 9 sets the trigger 7 to the state "1", and through the OR 5 element the delay element 20 sets the trigger 15 to the "1". The fourth pulse from the generator 41 via element 23, switch 6 and element 14 on (-) is the input of counter 19. The beam is deflected along the axis of the op-amp upward by one raster element, damping and illumination of the beam.

The video signal from the third input 75 of the device is converted by block 52 to a digital code, which is recorded in register 70 by a signal from the element OR 44. The signal from the imaging unit 36 records the contents of counters 18 and 19 into the register 72. The delayed signal from the element OR 44 through the delay element 68 the register is set to “0” 72, and the delay element 24 and the OR 30 element are set to trigger 0 at 0 ”.

The fourth pulse from the generator 41 through the element And 23, the element OR 42 and the counter 67 sets the trigger 60 to "0" and through the selector 38 the selection of the falling front and the delay element 61 is set to "0" the counter 67 and the trigger 65, through the element OR 47 installation in "0" of the trigger 7 and trigger 46, through the OR 10 element is set to "0" of the trigger 15, through the OR 31 element, the OR 63 element and the delay element 66 are set to "0" counter 55

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and register 70. Setting the “0” trigger 65 causes the signal shaper 37 to double the beam diameter of the CRT 35, and the device switches to reading with a large sampling and the reading cycle repeats. Overflow signals of counters 17 and 21 arrive at the element And 8 where the signal is generated, which through the OR element 2 sets the trigger 3 to ”0”, and the device stops reading.

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Reading graphic information can be stopped at any time by a signal from the second input 74 of the device.

With a fill factor of machine-building drawings of 3–7%, the accuracy and speed are four times as high as the redundancy of transmitted and stored discrete information decreases, respectively.

1180938

Claims (2)

1. DEVICE FOR READING GRAPHIC INFORMATION containing the first trigger, one input of which is the first input of the device, the other connected to the output of the first element OR, the output connected to one input of the first element AND, the other input connected to the first pulse generator, and the output connected to the first and second counters. lines and to the first frame counter, the second element And, the inputs of which are connected to the outputs of the first row counter and the second frame counter, and the output connected with one input of the first element OR and with row and frame counters, the other input of which is the second input of the device, the indicator whose inputs are connected to the outputs of the row counters and frame counters and the first driver of the signal whose input is connected to the blanking trigger, the first register whose inputs are soy 'dinene with the outputs of the first row counter and the second frame counter, and the output is the first output of the device, the second trigger, one input which is connected to the first delay element, and the output is connected to one input of the switch, the first group of elements is And, some inputs are connected to the first output of the third trigger, others are connected to the corresponding outputs of the switch, and the outputs are connected to the inputs of the second row counter, the second group of elements And , some inputs of which are connected to the second output of the third trigger, others are connected to the corresponding outputs of the switch, and outputs are connected to the inputs of the first frame counter, the second delay element connected to you Odom second OR gate and to one input of the third flip-flop, the other input of which is connected to the output of the third OR gate, a fourth OR gate, whose inputs are connected to outputs of the first and second counters lines and the first frame counter, and the output is connected to the third delay element and to one input of the fifth OR element, the other input of which is connected to the second signal conditioner, and the output is connected to one blanking trigger input, the sixth OR element, whose inputs are connected to the third and fourth elements delay, and the output is connected to another input of the blanking trigger and to one input of the fourth trigger, the output of which is the second output of the device, the pulse distributor, whose input is connected to the second pulse generator, and the output We are connected to the inputs of the second element OR, the first delay element and to one input □ about 1180938 the third element OR, the clock counter and the seventh element OR, while the output of the first row counter is connected to the input of the second frame counter ·, characterized in that, in order to improve the accuracy and speed of the device, it contains the third And element whose inputs are connected to the outputs of the second pulse generator and the first trigger, and the output is connected to another input of the switch, the eighth element OR, whose inputs are connected to the outputs of the first and second pulse generators, and the output connected to the inputs of the second signal conditioner and the fourth delay element, the fourth And element, one input of which is connected to the output of the third element And, the third signal conditioner whose input is the third input of the device, and the output is connected to the other inputs of the first register, the second signal conditioner and the fourth element And, the fifth delay element connected to the output of the fourth element AND, the ninth element OR, the inputs of which are connected to the outputs of the first pulse generator and the third element AND, and the output connected to one input of the clock counter, the fifth trigger, The output of which is connected to the third input of the third element AND, the sixth trigger, whose inputs are connected to the outputs of the distributor, pulses and clock counter, the first selector, whose input is connected to the output of the sixth trigger, the sixth delay element connected to the output of the first selector and another input of the counter cycles, the fifth element And, one input of which is connected to the first pulse generator, and the output is connected to one input of the seventh element OR, the tenth element OR, whose inputs are connected to the outputs of the sixth delay element seventh OR gate, and an output connected to one input of the second and fifth flip-flops and the other inputs of the third and the seventh element or the seventh delay element connected to the other input of the fifth flip-flop, the seventh flip-flop, one input of which is connected to the output of the sixth delay element, the eighth element delays connected to the output of the eighth element OR, the eleventh element OR, whose inputs are connected to the outputs of the seventh and eighth elements OR, the ninth delay element connected to the output of the eleventh element OR, the analog-to-digital conversion unit, one input of which is the third input of the device, and the others are connected to the outputs of the third signal generator and the ninth delay element, the second register, the inputs of which are connected to the outputs of the analog-to-digital conversion unit, the eighth and ninth elements behind holder, the tenth delay element connected to the output of the eighth element OR and to the input of the first register, the decoder, the inputs of which are connected to the second register, and the outputs are connected to the seventh delay element and to the other inputs of the seventh trigger and the fifth element And, the sixth element AND, inputs which is connected to the decoder and the fifth delay element, the eleventh delay element connected to the output of the sixth element And to another input of the fourth trigger, the fourth driver signals, the input of which is connected to the output of the seventh about the trigger, and the output is connected to the indicator, and the third register, the inputs of which are connected to the outputs of the first frame counter, the second row counter, the third driver and the tenth delay element, and the output is the third output of the device. 2. The device according to claim. ^, Characterized in that the analog-to-digital conversion unit contains a series-connected third pulse generator, a luminance generation counter, the other inputs of which are the first and the second inputs of the block; a digital-to-analog converter, a comparison element, the other input of which is the third input of the block, the fifth signal generator, the second selector and the seventh And element, the other input of which is connected to the output of the luminance formation counter, and the output is the output of the block. 1180938