SU1177838A1 - System for information transmission and check - Google Patents

Description

The invention relates to computing and the transfer of discrete information and can be used to exchange information between the input-output channel of a digital computer and 5

external devices geographically dispersed one with another.

The purpose of the invention is to increase the reliability and informativeness of the system.

FIG. 1 shows the structural

system diagram; ' in fig. 2 - block diagram of the recovery and control nodes; in fig. 3 is a block diagram of an external device controller; in fig. 4 is an example of a block diagram of an I / O device; in fig. 5 is a block diagram of the control unit of the controller; pas figs. 6 is a block diagram of a matching node for communication with the channel; in fig. 7 is a block diagram of a matching communication node with an external device; in fig. 8 - time diagram of recording information on the subscriber; in fig. 9 is a time chart of reading information from the subscriber.

The block diagram of the system (Fig. 1) 30 contains an input-output device 1, controllers 2 external devices, repeaters 3, which include the first block 4 of amplifiers-transmitters, the first node 5 of restoration 35 and control, the block b of elements OR, the second node 7 recovery and control, the second element OR 8, the second block 9 of amplifier-transmitters, amplifier-transceiver 10, trigger 40 11, element AND 12, encoder 13, element NOT 14, first element OR 15, amplifier-receiver 16, block 17 of amplifiers- transceivers, amplifier transceiver 18, internal tires 19 45

and 20 interfaces, failure lines 21 and 22, trigger installation line 23, failure reset line 24, trigger reset line 25, repeater failure line 26, previous repeater 50 relay layer line 27, internal bus 28 of the failed repeater number ,, bus 2931, interface, lines 32 and 33 of fault failure, lines 34 and 35 of failure, buses 36 and 37 of the number of the faulty repeater 55, bus 38 and 39 of the interface, buses 40 and 41 of communication with the channel of a digital computer.

The block diagram of the nodes of recovery and control (Fig. 2) contains a block 42 amplifiers receivers, register 43, block 44 elements AND, element OR 45, block 46 control modulo two, element And 47, the first element 48 delay, the second element 49 delay pulse generator 50, information bus 51, an internal interface bus 52 comprising a control bus 53 and information bus 54, a fault line 55.

The block diagram of the controller 2 of the external device (Fig. 3) contains the node 56 recovery and control, the first register 57 is given, the third register 58 own address, the second register 59 command, block 60 address comparison, node 61 control, switch 62, the fourth register 63 data , information bus 64, fault line 65, control bus 66, write lines 67 and 68, address equality line 69, address bus 70, status spike 71, switch control bus 72, information bus 73 and interface bus 39 control interface bus 75 data, record line 76, control bus 77, w Inu 78 data. For simplicity, FIG. 3, the connection lines of the control bits from the outputs of the registers 58 and 63 to the control unit 61, as well as the amplifier-transmitter of the output signals, are not shown. The block diagram of the input-output device 1 (FIG. 4) contains the first switch 79 of channel data, the first, second and third registers 80-82 for storing the command, data and subscriber amres, respectively, the fifth register 83 of the own address, the second address comparison block 84, the first matching node 85 for communicating with the channel, the fourth channel command register 86, the second data switch 87 to the channel, the second matching node 88 for communicating with an external device, the first comparison block 89, the sixth data register 90 from the external device, the recovery and control node 91 I bus 92 information, control bus 93, the switch 79 a control bus 94, channel bus 95 information, channel control bus 96, the line 97 addresses equality, lines 98-101 recording subscriber control bus 102, bus 103 subscriber information

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tires; 104 states, switch control control bus 105, control lines 106 and 107, write line 108, equality line 109, control bus 110, fault line 111, information bus 112, check digit line 113.

The block diagram of the controller's control unit 61 (FIG. 5) contains the first and second elements AND 114 and 115, the distributor 116 ^ trigger 117, the element OR 118, the third element And 119, the register 120 containing the triggers 121, the control unit 122 modulo two, 123 command decoder, logical block 124 containing AND 125 and 126 element, OR 127 element, AND 128-132 element, OR 133-134 element, distributor 116 lines 135-138, bus 66 lines 139-141, fault polling line 142 , lines 143 operations, address control line 144, total control digit line 145, subscriber response line 146, whether 147 of the control digit of the information, the lines 148-150 of issuing the address, status and information, respectively, bus 151 of the command code, element of the IPI-HE 152.

The block diagram of the first matching node 85 for communication with the channel (Fig. 6) contains a pulse generator 153, a fixed memory block 154, a microcommand register Γ55, a switch 156, an OR element 157, a synchronization line 158., the address 159 microbus; microinstructions, start line 161, bus 162 low-order bits of microcommand address, channel command bus 163, notification line 164, data request line 165 and 166, failure line 167, switch control bus 166, 156 bus, micro address, 16-com bus, address accumulator 170 modulo · two, line 171 counter olya

I

The block diagram of the second matching node 88 for communicating with an external device (FIG. 7) contains a switch 172, a modulo-two adder element 173, a request setting line 174, a synchronization line 175, a micro-bus 176, a high-order bus 177, ! bus 178 low-order bits of the address of the micro-command, the control discharge line 179, line 180 control77838 4

the main discharge lines 181-183, the corresponding C ₄ , C ^, P lines of the interface (FIGS. 8 and 9), the data request trigger 184, the waiting pulse generator 185, the control switch bus 182, 182, the micro-command bus 187, block 188 permanent memory, register 189 microcommands.

Timing diagrams (Fig. 8 and 9)

10 contain the C ₄ -C _e control lines, the data bus 8, the reset line K, the control line is not shown.

The abbreviations in FIG. 8 and 9: Addr. address, com. - team, Comp. - state, ,'- time delay.

The C ^ and C ^ control lines are designed to transmit control and information gates, respectively, over buses 29-31, 38 of the interface.

20 Line C ₂ control is designed to transmit the response strobe from • controller 2 to block 1 via buses 39, 30, 3! interface.

Line K is intended for transmission of a reset strobe through tires 29-31,

38 interface.

Bus 4 is designed to transmit information (data words) on tires 29-31, 38, 39 of the interface and

30 contains control information lines. nym discharge information. The nature of the information placed on the bus o / depends on the sequence of signals on the interface lines and has the purpose indicated above the notation of the pulses in FIG. 8 and 9.

Pulses 1 and 2 on line C, indicate the address of the subscriber and the command on the bus <3. Pulses 3 and 4 on the C-line indicate that the address and state of the subscriber are being read in controller 2, and there is no information on the c1 ^ bus.

The 1-PN line pulses indicate that there is data on the subscriber on the C bus when writing information to the subscriber, and when reading from the subscriber there is no information on the bus ό and is not indicated,

Coincidence impulse! on line C,) with a pulse on line C _g means the identification by controller 2 (subscriber) of its own address on lines 8 of bus 38.

Impulse 1 on the Su line. denotes the address of the subscriber on the lines of the bus 30, 31, 39. Pulses "data" means that there is an in5 on the lines

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subscriber formation. Pulse 2 on line C ₅ (FIG. 8) and the last pulse on line Cd (FIG. 9) indicate that the subscriber's status information is on the bus.

The device 1 input / output (figure 4); works as follows.

The DVR channel initiates a sequence of control signals for communication with device 1 and sends them to node 85 via bus 96. At the same time, the DVR channel is set to Junne 95 the address assigned to device I in the DVR channel program. Device 1 compares this address with its own address, stored in register 83, at comparison block 84. The equality signal addresses on line 97 enters the node 85, which produces a response control signals on the bus 102 and through the switch 87 produces the issuance of its own address from the register 83 on the bus 103 to the channel CVM.

The DVR channel checks the address of the device 1, coming via the US bus, for equality to the address given to device 1, and if they are equal, sets the channel command on the bus 95 together with the control signals on the bus 96. After receipt of the control signals via bus 96, identifying command on bus 95, node. 85 using a signal on line 101 records the command channel from the bus 95 to the register 86 and proceeds to its implementation. The command channel from the output of the register 86 enters the node 85, where it is decrypted. The command "Check'vvodvu" device 1 is not performed. The command "Refine status" node 85 using signals on the bus 105 controls the switch 87 to issue the number of the faulty repeater from the bus 36 and the updated status information of the device 1 from the bus 104 to the bus 103. Simultaneously with the issuance of information, the identification signals are sent to the DVR channel bus 102 denoting information on bus 103 and identifying the request for data transfer from device 1 to the digital computer channel. After issuing information from the bus 36 to the digital computer channel, node 85 generates a fault reset signal, which via line 107

enters node 88, and from node 88 to reset line 32 of faults in repeaters 3. After receiving a specified number of data words, the DVR channel responds to another request from device 1 and stops transmitting data by issuing the corresponding sequence over bus 96 to node 85. responding to a stop sequence node 85 using signals on the bus 105. controls the switch

87 for issuing an identification signal to the bus 102, informing the channel of the digital computer that the status information is on the bus 103, the channel of the digital computer receives the device state information! from tires 103 and finishes its work with device 1. At the command “Load registers”, node 85 issues a request for data to the DVR channel on bus 102 to load registers 80-82. The digital channel via the signal on bus 96 notifies device 1 that the data is on bus 95. Node 85 removes its request and, depending on the boot order, generates a recording signal

on one of the lines 98-100, which is used to write to the appropriate register 80-82, and then installs the next request for data on the bus 102. After loading all the registers 80-82, the digital channel, in response to the next request, stops the data transfer in the device 1, takes the word of the main state of the device 1, and then ends its work with it. By the “Record” command, the node 85 with a signal on line 107 starts the node 88. The node 88 builds its work in accordance with the timing diagram in FIG. 8. Knot

88 samples the subscriber by issuing signals along lines С *,

C ₂ bus 93 together with the issuance of the address and command of the subscriber from the registers 80 and 82 through the switch 79 to the bus 92 (bus of FIG. 8), and then reading the address of the subscriber using the third pulse issued to the line

bus 93. After that, node 88 waits for a response address from the subscriber, along with a signal on line C _{5 of} bus 31. Simultaneously with issuing the first

data words from register 81 to bus 92 node 88 via line 106 through node 85 and bus 102 issues a data request to the digital computer channel to load the register

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81 with the next data word from bus 95. The digital channel informs device 1 with a signal on bus 96 that the data is on bus 95. Node 85 removes the data request, notifies node 88 on line 107 about the execution of the request and records on line 99 information from the bus 95 in the register 81. The node 88 produces information from the register 81 to the bus 92, and on line 106 issues the next request for data. Information and control signals from the subscriber go via bus 31 to the recovery and monitoring node 91, which receives, restores the parameters and controls the signals on the bus lines 31. During the time determined by the interface delay T, the bus 88 from the node 91 enters the node 88 the response signal on line Sd, at the same time with which the address of the subscriber on the bus 112 enters the block 89 for comparison with the address of the subscriber stored in the register 82.

If the addresses are equal, the subscriber sample is considered successful and the data transfer to the subscriber continues in the same manner. If the addresses are not equal, the data transfer to the subscriber is stopped, but the interaction of device 1 with the digital computer channel continues. After issuing a specified number of data words to register 81, the DVR channel, in response to the next request, stops the data transfer in ’device 1, takes the ground state word from device 1 and then ends its work with it.

By the “Read” command, the node 85 as a signal on line 107 starts the node B8. The node 88 builds its operation in accordance with the timing diagram of FIG. 9. Node 88 samples the subscriber in the same way as the "Record" command. This, together with the transition to await a response from the local address unit 88 starts reading the subscriber information .from issuing signals on line C _r bus 93. Upon receipt of a response from the subscriber address is carried compares it with the address in registre.82 If the addresses are equal, then the sample the subscriber is considered successful and reading data from the subscriber continues. With the arrival of each next signal on the line to node 88, the subscriber’s data word from bus 112 is recorded in register 90 with a signal on line 108. At the same time, node 88 issues requests for data transmission that through line 106 through node 85 and bus 102 enter the channel Digital computer, Simultaneously with the issuance of requests, the block 88 signals through the bus 105 logically connects the output of the register 90 through the switch 87, to the bus. SW. After receiving a specified number of Data Words, the DVR channel in response to the next request stops the data transmission in device 1. Node 88 stops its operation. After that, the DVR channel takes the word of the main state of the device 1, and then ends its work with it. In case of address inequality, node 88 stops its work on reading data from the subscriber, but the device’s interaction with the DVR channel on issuing requests is saved and transferred to node 85. The DVR channel receiving the required number of queries stops the data transfer in device 1, accepts the ground state word device 1, and then stops working with it. On the "Read state" command, node 85 starts node 88, which generates a signal on line С <(fourth pulse on line С ^ bus 29 of FIG. 9) of bus 93, which reads the subscriber's state. The state of the subscriber, along with the signal on the line C $ (the fourth pulse on the SUS line 31 of Fig. 9) enters node 91 over time, and from there via bus 110 to node 88. Node 88 records subscriber status information in register 90 signal line 108-, and then issues a request through the node 85 on the bus 102 to the channel CVM. Simultaneously with the request, node 88 logically connects the output of register 90 to the SW bus. Channel DVR receives the data word from the bus 103, and then stops the data transfer in device 1, takes the word of the main state of device 1, and then uploads work with it. The "Read state" command is used by the DVR channel after the "Write" and "Read" commands. The command "Disable" node 85 starts node 88 ,. which gives a signal

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reset on the line To the bus 93, carrying out disconnection of subscribers from the interface. The DVR channel receives the status word of device 1, and then ends the operation with it. The "Disable" command is entered by the DVR channel into device 1 before transmitting data in the "Write" and "Read" commands, as well as after the unsatisfactory execution of the "Write", "Read" and "Read state" commands.

The control of information received from device 1 via bus 95 is carried out at node 85. Information in registers 80-83, 86 and 90 is monitored during the execution of channel commands using control elements included in the registers. The control is made at the moments of using the information in the registers. Signals of failure from these registers are received at node 85, where they participate in the formation of the main and updated status indicators of the device 1. Links for these faults are pa. FIG. 4 not shown. The control of signals on the lines of the interface on the bus 31 is carried out using the node 91 when they each arrive simultaneously on all the lines. Interface failure from node 91 via line 111, as well as repeater failure, through line 35 goes to node 88, and from it to node 85 for. generating the main and updated status indicators of the device 1 used by the digital computer channel for evaluating the results of command execution. Device 1 issues signals on the bus line ·

29 together with the control characteristic generated in the node 88 taking into account the signals on all lines of the bus 29 in accordance with the adopted method of control. To this end, the check digit information word from the bus 92 via line 113 enters the node 88, which outputs the total control signal together with the control signals to the bus 93.

The controller 2 (Fig. 3) works as follows.

The controller 2 builds its operation in accordance with the timing diagram of the signals in FIG. 8 and 9. Consider the controller operation using the example of the "Record" subscriber commands.

and "Count". The controller 2 is controlled by interface signals from the device via the interface bus 33 to the recovery and monitoring node 56, which receives, recovers and controls the incoming signals. The reconstructed interface signals from the interface output of block 56 via bus lines 66 (K, C ,,, C _g ) go to control unit 61, and the data word from information output of node 56 via bus 64 ((bus () goes to registers 57,

59 and block 60 address comparison.

In the subscriber sample stage, the subscriber address coming from device 1 is compared in block 60 with its own address stored in register 58. The comparison signal on line 69 goes to node 61, which, in case of equal addresses, interacts with device 1. Then when a subscriber command is received from device 1, node 61, using a signal on line 67, writes this command from bus 64 to register 59 and logically connects to the interface using bus 39. When a signal reads from the device, an address read signal (the third pulse on the line in Fig. 8 and 9), node 61 responds by issuing an address from register 58 and a signal to line C of bus 39. Line C _b enters bus 74, and address from register 58 enters bus 73 through switch 62, controlled by node 61 using signals over bus 72. If in the register

59 the "Read" command is stored, then simultaneously with the issuance of the address on the bus 39, the data word read signals are sent over the bus 77 to the peripheral device, and the first word of the data received from the peripheral device via the bus 63 is written to the register 63. Write to the register 63 is produced by a signal on the line 76. After issuing its own address to the bus 39, the controller proceeds to the command execution stage. The command "Read" control node 61, in response to each signal received via line C ^ of bus 66, produces ^ a data word from register 63 to bus 73 via switch 62. Each next data word is written to register 63 by a signal on line 76

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after the release of information from this register. Simultaneously with the issuance of the data word from register 63, the node 61 produces a signal on the line C _{2 of the} bus 74 and issuing the read signals for the tongue '77 to the peripheral device. The end of the reading of information is determined by the device 1, which stops the issuance of signals on the line C _a . The command "Record" node 61 in response to each signal received via line C _{g of the} interface, writes the data word from bus 64 to register 57 with a signal via line 68. A data word received from the interface to register 57 is output from the output of this register 57 bus 75 to the peripheral device. Node 61 via bus 77 outputs to the peripheral device control signals marking the recording mode and the arrival of each new data word. Stop recording apparatus 1 is determined, which stops issuing words uo data signal line and C ₂ interface communication with the controller 2. After the execution command "Write" and "Read" from the device 1 to C _L line interface receives a signal read state of the controller 2, the node 61 control in response to this signal, arriving via bus 66, provides status information from bus 71 to bus 73 and a signal to line C _e bus 74. After issuing the state to bus 39 controller 2 via the node 61 it is logically disconnected from the interface. Disconnecting the controller 2 from the interface is also performed with the arrival of a signal along the line H of the interface, through which the node 61 is reset to its initial state.

The controller 2 monitors the signals on the lines of the bus 38 interface and control information in the register 59 command. The signals on the interface lines are monitored using node 56 simultaneously on all lines for each new signal input. The failure signal from node 56 goes to the first input of node 61 via line 65. Information is monitored in command register 59 • at node 61 by control node 122. When failures are detected in the restraint 61, the state information is generated, which contains a detailed view of the failures and arrives at the bus 71. If a failure is detected in the "Record" command, then the node 61 outputs signals to write to the bus 77 and the peripheral device does not receive information from the register 57 via bus 75. Signals to bus 39 are issued together with the control characteristic generated in node 61 taking into account the signals on all lines of bus 39 in accordance with the accepted control method (for example, modulo two). To this end, the control bits of the words from the registers 58 and 63 go to the node 61, where the total control characteristic is formed, and via the control line of the bus 74 is provided to the interface bus 39.

Repeater 3 (Fig. 4) works as follows.

Interface signals, for example from. bus 29, go to the node 7 of the recovery and control, which carries out the reception, restoration of parameters and control of incoming signals. The reconstructed interface signals from the interface output of the node 7 to the lines of the bus 20 through the block 4 amplifiers-transmitters arrive at the bus lines 38, and through the block 6 OR elements and block 9 of the amplifiers-transmitters on the bus lines 30. Interface signals from the bus 39 enter the node 5 recovery and control, which receives, restores parameters and monitors incoming signals. · The reconstructed interface signals from the interface output of node 5 via bus lines 19 through block 6 of the OR elements and block 9 of amplifier-transmitters go to l SRI bus 30. Control signals on the interface lines is carried out during their admission. Upon detection of a failure of the signals on the interface lines, nodes 5 and 7 give fault signals on lines 21 and 22 to the OR element 8. The signal from the output of element 8 on line 23 sets the trigger 11 for failure, the alarm from the direct output of the trigger on line 26 through the element OR 15 and the amplifier-transmitter 18 is fed to the output of the repeater. The failure signal from the previous transponder enters the amplifier-receiver 16, and from its output - via line 27 through the element

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OR 16 and the amplifier-transmitter 18 is transmitted to the output of the repeater, and also via line 27 enters the input element HE 14, where it is inverted. The inverse signal of failure from the output of the element NOT 14 enters the input of the element 12 and permits the input of the encoder 13 and prohibits the passage of the reset signal of the failure to the reset input of the trigger 11 from the amplifier 10 via line 24, through the element 12, line 25, and also prohibits the encoder 13 issuing a code to the bus 28. When the trigger 11 is set and the code has been authorized to issue the code, the encoder 13 encodes the repeater number into a binary code and, via the bus 28 through the amplifier block 17, receives the transmitters at the repeater output. The code number of the next repeater, coming through the bus 37 through the block 17 amplifiers-transceivers, is transmitted to the same output of the repeater. The fault reset signal from the previous repeater or from device 1 to the input of the amplifier-transceiver 10 is amplified in power and transmitted further to the output of the repeater, and also through line 24 to the input of the I 12 element.

Nodes 5, 7, 56, and 91, recovery and control (Fig. 2) work as follows.

Signals from the interface lines, arriving in the form of pulses synchronously and in-phase (Fig. 8 and. 9), pass through the receiver amplifiers block 42 and arrive at the information inputs of the register 43, as well as at the inputs of the OR element 45. The OR element 45 selects at its output the first of the incoming signals, which is delayed by the first element 48 of the delay at a time, consisting of the skewing of the interface signals and presetting information at the information input of the register 43. The skew is the heterogeneity of the signals from the interface lines ca at the output of the block 42 receiver amplifiers. The skewing of interface signals occurs when these signals pass through amplifiers, transmitters, cable lines, amplifiers, receivers due to technological variation of delays in the indicated elements. The signal from the output of the first delay element 48 is fed to the synchronization input of register 43 and, with its front, records interface signals from block 42 to register 43. In addition, the signal from the output of the first delay element 48 passes through the second delay element 49 and starts its front block 50, forming at its output a signal in accordance with the desired duration of the interface signals. The second element 49 of the delay is delayed signal at a time determined by the sum of the delays of the inclusion of the register 43 and the block 46 of the control. The signal from the output of the imaging unit 50 is fed to the control input of the I unit 44 and outputs the interface line signals stored in the register 43 to the bus 52. The bus 52 contains the bus 53 data words corresponding to the niche (Fig. 8 and 9) and the bus 54 control lines, containing the line C ^ -C ^, K (Fig ·. 8 and 9). The signal from the output of the imaging unit 50 is also supplied to the first input of the element And 47 generates a failure signal from the output of the control unit 46 to the failure line 55. Control unit 46 ’controls the information at the output of register 43 in accordance with the accepted control method (for example, modulo two). The signal failure from the output of the block 46 is fed to the second input element And 47.

The control unit 61 (FIG. 5) operates as follows.

Node 61 operates in accordance. with time diagrams of interface signals (Fig. 8 and 9). Interface signals on lines · 139-141 buses

66 enters node 61. Line 139 corresponds to line C _A ·, lines 140 line C _g , lines 141 - line o (. When the signals of lines 139 and 140 coincide, the signal at the output of the second element I 115 appears, which arrives at the trigger trigger input 117 and writes the result of the address comparison to the trigger 117. The result of the address comparison on line 69 is fed to the information input of the trigger 117. If the comparison result is positive, then the trigger 117 is set to one.

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It also allows the distributor 116 to work with a signal from its direct output, and also allows the signal from the line 65 to pass through the element 119 to set the first trigger 121 in the register 120. The distributor 116 carries out the serial distribution of the signals on the line 139 to its outputs. Distributed divider 116 has four states to represent the four signals on line 135 (the lines of FIGS. 8 and 9). The change of states of the distributor 116 is made at the moment of the end of the signal on the line 139. The state signals of the distributor 116 are output on the line 135-138. Thus, if there is permission from the trigger 1 1 7, the distributor 116 after the termination of the first signal on the line

139 is set to the first state. The signal of the second state on line 136 enters the block 124 logical, where it allows the passage of the third signal from line 139 to the data recording line 76 and the bus 77 through the elements 131 and. 133 in the subscriber's command “Count”, to the control line 145 through the elements 128.125, 127 and the bus subscriber’s response line G46 through the elements 131, 133, 134, to the line 148 for issuing the bus address 72 through the element 128. the input of block 124 produces signals on these lines, and then the distributor 116 is transferred from the second state to the third. The signal of the third state of the distributor 116 enters the block 24 logical and allows the generation in it of the control signals for the execution of the subscriber’s commands depending on the command code received in width 151. The output "signal: block 124 is generated using the signals arriving at elements And 130-132 of the block 124 from line

140 (line C ^ fig. 8 and 9) tires 66.

The command code on the bus 151 comes <to the input of the decoder 123, which in

depending on the operation contained in the code, the command generates a signal of this operation on one of its outputs. The operation signals from the decoder 123 по via bus lines 143 are received at block 124. The “Read” operation signal is fed to the bus

177 and to the input of the element 130, where it permits the passage of signals from the line 140 to its output. Signals from

₅ outputs of the element I. 130 arrive on the line 150 of information output and through the OR element 133 arrive on the recording line 76 and the bus 77 reading line, through the OR element 134 post—

0 fall on line 146 of the response, and also ί give the value of the check digit from line 147 through; elements 126 and 127 to line 145 of the control ,. The “Record” operation signal is sent to bus 77 and to output element I 132, where it permits the passage of signals from line 140 to its output, which is connected to line 68 and the recording line of bus 77. When a signal arrives from line 139 to element I 129 at its output, a signal is generated, which is fed to the state output line 149 and through the OR element 134 to the line 146

; response bus 74. After the end of the signal on line 139, the valve 16 enters the fourth state. The formation of signals at the output of block 124 is terminated. The signal four) of that state passes through line 138, through the OR element 118 and resets the trigger 117. Resetting the trigger 117 causes the 1 GB distributor to reset to the initial state when there are no signals on the lines 135-138. The arrival of the signal on the line 141 at any time causes a reset of the trigger 117, the distributor 116, and the register 120.

Block I24 generates signals on the control line 145 in the second and. the third state of the dispenser 116.

In the second state of the distributor ·

116 when a signal arrives on line .139 at block 124 on line 145 of the con-trol, the value of the check digit is output from line 144 through elements 125 and 127. In the third state of the distributor 116, when signals are received through line 140, block 124 in the operation "Read" on the control line 145, the value of the check digit from the line 147 is output through elements 126 and 127. · The command code on the bus 151 is monitored using the control unit 122. The control result is polled by the signal of the third state of the distributor

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116 via line 138. In the event of a failure, the signal from the output of node 122 installs the second trigger 121 of register 120. Element OR 152 5

checks the contents of register 120 and, if there are failures in the "Write" operation, then the signal from the output of element 152 prohibits the output of recording signals to the output of element 1032, and from it to the outputs of block 124.

Nodes 85 and 88 of the input-output device 1 (FIGS. 6 and 7) are based on the principle of microprogram control, 5 control, in accordance with which the control signals are stored in a block of permanent memory in the form of a microprogram. The microcommands that make up the microprogram are organized in sequence by forming the address of the Next microcommand.

This address is obtained as follows: the highest part of the address is indicated in the microcommand itself using 25 signals on buses 160 and 177, and the younger part of the address on buses 162 and 178 is either the address specified in the microcommand using signals on tires 169 and 187, or 30 address determined by the state of one of the groups of signals at the information inputs of the switches 156 and 172. The use of the younger part of the address is solved by using signals on the buses 168 and 186 of the control switches 156 and 172. The address on the buses 169 and 187 used for unconditional transitions in the firmware. The address indicated by the state of the input 40 signals of nodes 85 and 88 is used for conditional transitions in the firmware, and depending on the state of the signals on the lines of the switched group, branching in two directions is possible in two directions.

Matching node 85 connection with the channel. scrap works as follows.

After turning on the power, the device sets the initial state of node 85, in which the micro-command register 155 is cleared ·, and the upper group of ^{55 is} logically connected to the buses of the 162 lower-order bits of the address of the next micro-command ^.

. interface from the bus 96 control channel. From this point in time, micro-commands are continuously read from the permanent memory block 154 and are written to the micro-register register 155 by signals on the synchronization line 158 from the generator 153. Thus, node 85 is set to wait for signals to initiate exchange with the DVR channel from the older group of bus lines 96, which is implemented by looping the microprogram on one microcommand to the zero address. When these initialization signals arrive, the firmware analyzes the order in which they arrive, issues response signals to the digital computer channel via the subscriber control bus 102, and then signals the bus 186 controls the switch 172 to check the signals on the lower bus lines 96 along with the address equality signal 97 address comparison.

As a result of the address comparison, the firmware sets the signals on bus 105 to control the switch 87 to issue the subscriber's response address from register 83 to bus 103, sets the response signals on bus 102 and proceeds to check the group of signals on the bus 96 days to determine when a channel command is transmitted on the bus 95

When signals are received on bus 96 identifying the transmission of a channel command, the firmware generates a signal on line 101 to write the channel command to register 86, and then sets the status information of the I / O device 1 on bus 104, sets the control signals of switch 87 on bus 105 to logical connection of the bus 104 to the bus 103, and also gives response signals to the bus 102, indicating the transfer of the state of the device 1 I / o to the channel.

After the receipt of response signals from the channel via bus 96, the microprogram, using signals from bus 168, checks the command code on bus 163 to decrypt it. Depending on the command code, the address on the bus 162 changes and in the firmware there is a branch to the command-run subroutines. For teams that interact with

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an I / O device 1 with controllers 2, a signal is set on start line 161 to allow operation of node 88. Then firmware 5

proceeds to check the signals on the bus 96.

The operation of the node 85 will consider the example of the command "Refine status". ten

The command "Refine status" firmware using signals on bus 105 connects bus 36 of the number of the faulty repeater to subscriber information bus 103 and via line 165 through the OR element 157 outputs a data request signal to bus 102. After receiving a notification signal on bus 96 about receiving information ₂ θ the firmware resets the request signal on line 165 and waits for a response reset of the alert signal on bus 96 to reset the data request signal on line 165. ₂ 5

Together with the re-installation of the request for the firmware data via signals on the bus 105, it is logically connected- includes the updated status information from the bus 104 to the bus 103. With 30

NTRY alert response signal on the bus 96 next firmware issues a request for data line .165, in response to 'the request bus 96 enters shutdown sequence at which the firmware sbra ^ ³ ik- request on line 165 to the bus 104 sets the status information to the base unit 1, and then, via bus 102, issues a signal indicating the transmission of the state. Then the channel of the digital computer ⁴ θ on the bus 96 generates a disconnect sequence from the interface, in which the firmware terminates the execution of the channel command, resets the signals on all outputs of the register 155 ⁴⁵

microcommands and node 85 is set to wait for initialization signals to exchange with the digital drive channel from bus 96. Note that the data request signal on line 165 forms a ⁵ θ · microprogram only for the "Refine status", "Load registers" commands, a signal on the line 161 start-ups are generated by the firmware for all commands except "Check I / O", 55 "Load registers". The signal on the start line 161 in the Refine State command is generated by the microprogram after transmitting information from the bus 36 to the digital computer channel in order to start the node 88 to generate a signal on the fault reset line 32 in repeaters 3.

Node 88 connection with an external device operates as follows.

In the initial state, the microcommand address is determined by the command code on the bus 163, the line group of which is logically connected to the 178 lower order address bus of the next microcommand using the switch 172, the signal on the start line 161 is absent, which prohibits the generator of 185 synchronizing pulses and resets the microcommand register 189 .

When a signal arrives on the start 161, the waiting generator of 185 clock pulses begins to work.

From this point in time, micro-commands are continuously read from the constant-memory unit 188 and recorded in the micro-command register 189 'via signals on the synchronization line 175 from the generator 185. Depending on the command code on the bus 163, the firmware is forwarded to the appropriate subroutine to perform teams.

Further work unit 88 considered-. Rome on the example of the command "Write".

With the "Write" command, the firmware builds its work according to the time chart of the recording (Fig. 8).

For this, the firmware generates signals C1 and C ₂ on lines 181 and 182, as well as signals on bus 94 control switch 79 (Fig. 4) in order to logically connect the address of the command and data from registers 8-2, 80,

81 respectively to the data lines of! Bus 29. (} At the same time, with the data word being output to the microprocess bus 29, the signal via the I74 line sets the data request trigger 184, from which output 166 to the node 88 and further to the DVM channel a request for the next data word is issued.

In response to this request from the channel of the digital computer, a data word and a signal are received on the alert line 164, which resets the trigger 184.

After issuing the third signal to the Ιδί line, the firmware checks the receipt of the address

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subscriber For this purpose, lines 35, 109-111 use the 'signals of the bus 186 through the switch 172 to logically connect to the bus 178 and set the address of the next micro-command. As a result of analyzing these signals, a branching in 16 directions is performed in the firmware. Verification of the subscriber's address receipt consists in checking the signal on the line by the microprogram: 109 address comparison. The presence of the signal ya of this line corresponds to the equality of the addresses supplied to the comparison block 89. In the absence of signals on lines 35 and 111 of failure, node 88 continues its work on data transfer. If there are signals on lines 35 and 111 of failure, the signals on lines 174, 179-183 are stopped, and on line 167 a failure signal is generated, which is used by node 85 to stop operation of node 88 by resetting the signal on start line 161, as well as to issue requests data on line 165 (Fig.6) in order to maintain the interaction, the device 1 input-output channel digital computers. .

When resetting the signal from the start line 161, the micro-command register 189 is reset, and the generator 185 stops its operation.

When issuing information on data lines from a bus / 29 using modulator 2 element 173, a direct or inverse check digit is output from line 113 to line 180. If the number of signals is 01.02 on lines 181 and 182 is even, then the inversion is not produced, otherwise inverted. Inverting is carried out in the presence of a signal on line 179a, at which the signals ..on lines 179a,

113 are summed modulo 2. The result of this summation is given by the signal on line 179 in line 180.

In controllers 2, the inverse values of control bits from registers 58 and 63 are connected to node 61-control using lines 144 and 147,

The device works as follows.

The operation of the device is controlled by the DVR channel using the commands "Check I / O", "Refine status", "Load registers", "Write", "Read", "Read status", "Disable". The interaction of the DVR channel with the device is carried out through a standard interface formed by bus system 40 and 41, with asynchronous signal interaction by the request-response principle and is carried out using an input-output device 1.

The operation of the device is carried out in two stages. At the first stage, the DVR channel uses the "Check I / O" and "Refine Status" commands to check the bus lines 40 and 41 of the standard interface, check the status of the I / O device 1 and check the code on the bus 36. If the I / O is good, and the digital computer using the command "Load registers" enters into the registers 80-82 the subscriber's address, the subscriber's command and the first data word used by the command of the channel "Write". This concludes the first phase of work.

At the second stage, the input device 1 interacts with the digital computer channel and the external device 2 controllers (subscribers). · This interaction is carried out using the "Record",. "Read", "Read state", "Disable" channel commands. Using the "Record" and "Read" commands of the input-output device 1, it begins its interaction with controller 2, selects the subscriber, and then, without waiting for the subscriber's response {from controller 2), it exchanges information between the digital computer channel and controller 2, whose address is indicated by the address of the subscriber. Then, the I / O device 1 checks the result of the subscriber sampling and, if it was successful, the I / O device 1 continues its interaction with the controller 2 for information exchange, otherwise this interaction stops. The interaction of the I / O device 1 with the digital drive channel is preserved regardless of the result of sampling abo- ₍ penta until the end of the array length

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data. The digital channel determines the end of the length of the data array, stops the interaction of the I input device with the controller 2 by the exchange of information and checks the result of executing the "Write", "Read" channel commands by analyzing the main state word of the I / O device 1. If the result of executing these commands is satisfactory, then the digital computer channel using the read state command of the channel reads the state of controller 2 into the digital computer channel to check the result of the write command of the channel write or read by controller 2, otherwise the digital computer channel using the command channel "Disconnect" produces a logical disconnection of the controller 2 from the device 1 input-output. If the “Read state” channel command is executed by the I / O device 1, then the controller 2 is also logically disconnected from the I / O device 1,

In the opposite case, the digital computer channel makes such a shutdown using the “Disable” channel command. At this, the interaction of the digital computer channel with the controller 2 for information exchange ends, and the second stage of operation of the device ends.

The device 1 interacts with the controllers 2 external devices through a serial ('(ring)) synchronous data channel with a unidirectional closed circuit formed by device 1, bus systems 29-31 interfaces, repeaters 3. This channel has a “branch from repeaters 3 to each controller, made using tires 38 and 39 of the interface. The interaction of the device I input-output controllers 2 external devices is carried out in accordance with the timing diagrams (Fig. 8 and 9). The information flow on the bus c) together with the synchronization signals on the C ^ / and C _g lines, spreads in parallel in the form of pulses and passes from the I / O device 1 through the buses 29 and 30 through the repeaters 2 and through the bus 31 again enters the input device 1 - withdrawal. Delayed Pace 24

The active synchronous channel is the same for all controllers 2 interacting with an I / O device 1. The delay from the moment the signals are received by the input-output device 1 to the bus 29 until the device receives them from the bus 31 is time T (Figures 8 and 9). The interface signals are branched off from each repeater 3 and, via the interface bus 38, are sent to controllers 2. Controllers 2, which identify their address on the lines p | bus 38, receives the command in the register 59 / Fig. H) ¹ and logically connects its outputs via bus 39 via repeater 3 to buses 30 and 31 of the interface, which then sends information along with the signal via the C $ line. At this time, the bus lines 30 and 31 of the interface simultaneously contain signals from both the I / O device 1 and the controllers 2, which must be separated in time to ensure normal operation of the recovery and control nodes 5 and 7 in the repeaters 3 as well as the .91 recovery and control node in an I / O device. Exploding · _"hr said signals carried in time due to the natural delay. signals in the cables of buses 38 and 39 and the equipment of the controller 2.

In this case, the total delay should be greater than the duration of the interface signals. The adjustment of the total delay can be made in the controller 2 using the element 49 of the delay.

When transmitting signals through the serial synchronous interface, the channel restores their parameters and monitors the signals on all interface lines, carried out with the help of nodes 5, 7, 56 and 91 of restoration and control, which are part of repeaters 3, controllers 2 and input-output device 1 .

For control, any of the known methods can be used, for example, modulo-two control. For the purpose of monitoring along interface lines, a control signal is issued along with working signals, which supplements the number of signals on the interface lines to odd. With front / che interface signals on buses 29 and 30 through

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26 transponders 3 failure, arisen on the interface lines, spreads from the place of its origin further in the direction of signal transmission and is recorded in all subsequent repeaters 3 on trigger 11. Fault signals from repeaters 3 through fault line 34 propagate through all subsequent repeaters 3 and through fault line 35 from the last repeater 3 enter the I / O device. When assembled in repeaters 3, they issue the number of the faulty repeater to bus 36 to I / O device 1, depending on their priorities, which are determined by the order in which the repeaters 3 are connected to I / O device 1. The highest priority is given to the first repeater 3 connected to the I / O device 1 via the interface bus 29. Thus, on the bus 36 is issued the number of the defective repeater 3, the closest to the device 1 I / o. The issuance of codes from the rest of the repeaters 3 that have detected a failure is prohibited by the “Failure” signal on line 34, received from the relay 3 that is closest to the I / O device of the repeater 3. The number of the faulty repeater is distributed via tires 37 through repeaters 3 in the direction from the last repeater 3 to the first one, and then via bus 36 enters input-output device 1.

The DVR channel with the help of the Refine State channel command checks the code on Shia 36 and a signal from I / O device 1 on line 43 clears the fault in repeaters 3. Signal 32 passes through repeaters 3, where it recovers from power, resets triggers 11 crashes and

on line 33 issued to the next relay 3.

In addition to monitoring signals on the bus interface lines 29-31, 38, and 39, the transmission and storage of information is monitored in the input-output device 1 and controller 2, which also uses modulo-2 control. Information on errors and faults in device 1 and controllers 2 is available to the digital computer channel, which reads this information to evaluate the results of command execution of the channel of the I / O device 1 and controllers 2.

Thus, in the proposed system, information is exchanged using the input-output device 1 between the digital computer channel and the controllers 2 external devices. In this case, the DVR channel produces both the recording of information in the controllers of 2 external devices, and the reading of information from these controllers.

Improving the reliability of the system is achieved by end-to-end monitoring of interface signals in repeaters 3, controllers 2 and input-output device 1 simultaneously on all bus lines 29-31, 38 and 39, both information and control.

In addition, the reliability increase is achieved due to the priority issue of the number of the faulty repeater to the corresponding bus from the repeater closest to the place of occurrence of the failure, which excludes the issue of the repeater number from several repeaters 3 on the same bus code at the same time in which the faults are fixed.

Improving the informativeness of the system is achieved by restoring the time parameters of the interface signals in repeaters 3, controllers 2 and input-output device 1.

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Claims (5)

1. SYSTEM FOR TRANSMISSION AND CONTROL OF INFORMATION, containing sequentially connected repeaters, each of which contains an amplifier-receiver, the first element OR, an encoder, a trigger, the output of which is connected to the first input of the encoder, the input of the amplifier-receiver is the first input of the repeater, the first, second and the third outputs of each previous repeater are connected respectively to the first, second and third inputs of the subsequent repeater, which is aimed at increasing the reliability and informativeness of the system, input-output device and external device controllers are introduced by the number of repeaters, the first input and output of the input-output device are respectively the first input and output of the system, the second and third outputs of the input-output device are connected respectively to the second and third inputs of the first repeater, the fourth outputs of each subsequent the repeater is connected to the fourth inputs of the previous repeater, the fourth outputs of the first repeater are connected to the second inputs! I / O devices, the first and third outputs of the last repeater are connected to the third and fourth, respectively! I / O device inputs, fifth outputs and inputs of each transponder are connected respectively to the first inputs and outputs of the corresponding controller, the second and third outputs and the second inputs of the controllers are respectively the second and third outputs! and second! Amplifier-transmitter units, recovery and control units, OR unit, second OR element, AND element, NOT element, amplifier / transceiver unit, amplifier-transmitter, amplifier-transceiver, first and second outputs of the first node recovery and control are connected respectively with the first inputs! block of elements OR and the second element OR, the first and second outputs of the second node recovery and control are connected respectively to the second! inputs ^{of the} block of elements OR and the second element OR, the inputs of the first and second nodes of restoration and control are respectively the fifth and third! the inputs of the repeaters, the first outputs of the second node of the recovery and control are connected to the input of the first block of amplifier transmitters, the outputs of which are FIFTH! the repeater outputs, the outputs of the block of elements OR through the second (3 (eight the amplifier / transmitter unit is connected to the third outputs of the repeaters, the output of the second, OR element is connected to the first trigger input, the output of which is connected to the first inputs of the AND element and the first OR element, the amplifier output of the receiver is connected directly to the second input of the first OR element and - with the second inputs of the element And and the encoder, the outputs of which are connected to the first inputs of the block of amplifiers for transmitters, the second outputs and inputs of which are respectively the fourth outputs and the inputs of retransmission insulators, the output of the first OR gate is connected through a transmitter amplifier to the first output of each repeater, the first output and input are respectively usilitelyapriemoperedatchika second output and the input of the repeater usilitelyapriemoperedatchika second output connected to a third input of AND gate whose output is connected to the second input of the flip-flop, 2, System pop. 1, characterized in that the external device controller contains a control node, a recovery and control node, registers, a comparison unit, a switch, the first and second outputs of the recovery and control node are connected, respectively, to the first and. the second inputs of the control unit, the third outputs of the recovery and control unit are connected to the first inputs of the first and second registers and the comparison unit, the outputs of the second register and the comparison unit are connected respectively to the third and fourth inputs of the control unit, the outputs of the first register are the second outputs of the controller, the outputs of the third register are connected with the second inputs of the comparison unit and with the first inputs of the switch, the first and second outputs of the control unit are connected to the second inputs of the second and first registers, respectively moat, third and fourth outputs of the control node connected respectively to the second and third inputs of the switch, which outputs a fifth output control unit is the first controller output, a sixth control output node coupled to the first 1177838 the input of the fourth register, the outputs of which are connected to the fourth inputs of the switch; the seventh outputs of the control unit are the third outputs of the controller; the inputs of the recovery and control node and the second inputs of the fourth register are respectively the first and second inputs of the controller. 3. System by π. 1, characterized in that the I / O device contains matching nodes, switches, registers, comparison blocks, a recovery and control node, the outputs of the first and second registers are connected respectively to the first and second inputs of the first switch, the outputs of the third the register is connected to the third inputs of the first switch and the first inputs of the first comparison unit, the outputs of the fourth register are connected to the first inputs of the second switch and the second comparison unit, the output of which is connected to the first input of the first matching the first node, the first, second, third and fourth outputs of which are connected to the first inputs of the first, second, third and fifth registers respectively, the outputs of the fifth register are connected to the second inputs of the first matching node, the fifth and sixth outputs of which are connected to the second and third inputs of the second switch whose outputs and the seventh output of the first matching node are the first output of an input / output device, the output of the first comparison unit is connected to the first input of the second matching node, the first and second outputs Odes of the recovery control node are connected, respectively, to the second and third inputs of the second matching node, the third outputs of the recovery and control node are connected to the second inputs of the first comparison unit and the first inputs of the sixth register, the outputs of which are connected to the fourth inputs of the second switch, the first and second the outputs of the second matching node are connected respectively to the second input of the sixth register and the third input of the first matching node, the eighth output of which is connected to the fourth input of the second according to present node tre1I77838 the third output of which is the second output of the I / O device, the fourth output of the second matching node is connected to the fourth input of the first switch, the outputs of which and the fifth output of the second matching node are the third outputs of the input / output device, one of the outputs of the first switch is connected to the fifth input of the second matching the node, the second inputs of the first, second, third and fifth registers, the fourth and fifth inputs of the first matching node and the second inputs of the second comparison unit are the first input of the device vv The single input, the fourth inputs of the second switch are the second inputs of the input / output device, the sixth input of the second matching node is the third input of the input / output device, the inputs of the recovery and monitoring node are the fourth inputs of the input / output device. 4. The system of PP. 1-3, characterized in that the node recovery and control contains a block of amplifiers-receivers, register element OR, delay elements, pulse shaper, element And, block elements And, the control unit modulo two, the outputs of the block of amplifiers-receivers connected to the first inputs the register and the OR element, the output of which is connected through the first delay element to the second input of the register and the input of the second delay element, the output of which is connected through the pulse shaper to the first inputs of the AND element and the block of AND elements whose outputs are are first output node and recovery control register outputs are the outputs of the third recovery unit and the control and connected directly to the second inputs of block elements And through the control unit modulo two - with the second input of the element I, the output of which is the second output of the recovery and monitoring node, the inputs of the amplifier / receiver unit are the inputs of the recovery and monitoring node. 5. The system of claim 2, wherein the control unit comprises a decoder, a modulo-two control unit, a distributor, AND elements, OR elements, an OR-NOT element, a trigger, a register, and a logic unit, the first inputs of the first and second elements And, the distributor and the logical unit are combined and are the first input of the first inputs of the control node, the second inputs of the second element And logical. block are combined and are the second input of the first inputs of the control node, the first inputs of the OR element and the register are combined and are the third input of the first inputs of the control node, the output of the second element AND is connected to the first trigger input, the second input of which is • the fourth input of the control unit, the first input of the third, And element is the second input of the control node, the output of the OR element is connected to the third input of the trigger, the output of which is connected to the second inputs of the distributor and the third element And, the first output of the distributor is connected to the second input of the first element And, the output of which is the first output of the control unit, the second output of the distributor is connected to the second input of the OR element, the third and fourth outputs of the distributor are connected respectively to the third and fourth inputs of the log The third unit And the output of the third element is connected to the second register input, the outputs of which are the third outputs of the control unit and connected to the inputs of the element OR NOT, the output of which is connected to the fifth input of the logic unit, the inputs of the unit modulo two and the decoder are combined and are the third inputs the control unit, the outputs of the decoder are connected to the fifth inputs of the logic unit, the first output of the logic unit is connected to the second input of the control unit modulo two, the output of which is connected to the third input of the register, the second, three Lu, fourth, fifth and sixth outputs logiches- Whose unit are the second, fourth, fifth, sixth, and seventh outputs of the control unit, the sixth and seventh inputs of the logic unit, respectively, are the fifth and sixth inputs of the control unit. one 1177838