SU1172013A1 - Servo analog-to-digital converter - Google Patents

Abstract

CONTINUOUS ANALOG-DIGITAL CONVERTER containing a comparator, the first input of which is connected to the input bus, and the output / control element - with the first input of the reversing counter, that, in order to increase the accuracy of the conversion, an analog sum block and two integrating elements are introduced into it, the input of the first integrating element is connected to the control element, the input of the second The integrating element is connected to the output of a digital-to-analog converter, and the outputs of the first and second integrating elements are connected to the corresponding inputs of the analog summing unit, the output of which is connected to the second comparator input, the second input of the control element is connected to the clock pulse bus, and the output buses are connected to the reverse outputs counter.

Description

one

The invention relates to radio engineering and can be used to convert analog signals into digital code.

The purpose of the invention is to improve the accuracy of the conversion.

The drawing shows a block diagram of the proposed device.

The device contains a comparator 1 control element 2, a reversible counter 3, a digital-to-analog converter 4, the first 5 and the second 6 integrating elements, block 7 is analogous to the summation.

In the proposed device, the comparator 1 is connected to the input signal bus, and the second input is connected to the output of the analog summing unit 7, the comparator output is connected via the control unit 2 to the first input of the reversing counter 3, the outputs of which are connected to the inputs of the digital analog converter 4. Reverse counter 3 input the first integrating element 5 is connected to the input of an analog summation unit 7, the second input of which the second integrating element 6 is connected to the output of a digital-to-analog converter 4. On unity control inputs elzmenta 2 and 3 are supplied to down counter clock signals.

The device works as follows.

132.

The input signal is fed to the first input of the comparator 1, the second input of which receives a signal from the output of the analog sum block 7. According to the comparison results, control element 2 outputs a signal to the control input of the reversible counter 3. If the voltage from block 7 is greater than the input signal, then

The control unit 2 causes the subtraction signal to the reversible counter and the addition signal if the input voltage is greater than the voltage from block 7. The code from the reversing output

the counter is fed to the input of a digital-to-analog converter, the signal from the output of which is fed to the input of the second integrating element 6, which limits the rate of increase of the signal. Therefore, the emissions contained in the output of the D / A converter do not feed into analog summing unit 7, to the second input of which the signal from the first integrating element 5, which is switched on in a certain way, and whose parameters are chosen so that its output signal is summed up block 6, forms the ideal stage at the output of block 7, since the inclusion of two integrating elements, complementary to each other, makes it possible to exclude

emissions from the output of the DAC and maintain speed.

Claims (1)

The NEXT ANALOG-DIGITAL CONVERTER containing a comparator, the first input of which is connected to the input bus, and the output through the control element is to the first input of the reversible counter, the second input of which is connected to the clock bus Zktact О- ---- · pulses, and the outputs are with the inputs of the digital-to-analog converter, characterized in that, in order to increase the conversion accuracy, an analog summing unit and two integrating elements are introduced into it, the input of the first integrating element is connected to the output of the control element, the input the second integrating element is connected to the output of the digital-to-analog converter, and the outputs of the first and second integrating elements are connected to the corresponding inputs of the analog summing unit, the output of which is connected to the second input m comparator, the second input of the control element is connected with the bus clock pulses and the output bus connected to outputs of the reversible counter.