SU1167604A1 - Calculating device - Google Patents

Abstract

COMPUTATIONAL DEVICE containing the first, second and third shift registers, first, second and third adders calculators, first and second switches, with the low-order outputs of the first, second and third shift registers connected to the first inputs of the operands of the first, second and third adders, respectively subtracters, the outputs of the first, second and third adders-subtractors are connected to the information inputs of the first, second and third shift registers, respectively, and the first and volt bit outputs The shift registers are connected to the inputs of the first and second switches, respectively, the second input of the operands of the third adder-subtractor is connected to the information input of the device, the output of the first adder-subtractor is connected to the information output of the device, in order to expand the functional capabilities of the device beyond by multiplying and dividing the coordinates of the vector by a constant, the device contains the fourth and fifth shift registers, the switches from the third to the seventh, the fourth adder-calculus teller, subtractor, delay element and control unit containing decoder, first, second and third triggers, clock generator, binary counter, first and second elements 2-2AND-OR, and EXCLUSIVE OR element whose trigger is connected to the zero input of the first trigger The unit input of which is connected to the output of the clock generator and the clock input of the binary counter, the counting input of which is connected to the one (the first output of the first trigger, the blue clock input of the second trigger and the first input of the first 2-2I-OR, the second input of which is connected to the output of the second 2-2I-OR element, the first input of which is connected to the first output of the decoder, the second output of which is connected to: the second input of the second 2-2I element, zero output of the first trigger is connected to the third input of the first element 2-2 and-OR and to the synchronizing input of the third trigger, the single input of which is connected to the third output of the decoder and to the single input of the second trigger, the single output of which is connected to the first input of the EXCLUSIVE OR element, the second the input of which is connected to the unit output of the third trigger and to the fourth input of the first element 2-2 and -OR, and the first unit output of the first trigger is connected to the control

Description

the inputs of the fourth, fifth, sixth and seventh switches, the output of the first 2-2I-OR element is connected to the control to the inputs of the first, second and third calculator adders, the single output of the third flip-flop is connected to the control input of the fourth subtractor , the first input of the decoder is connected to the output of the second adder-subtractor, the second input of the decoder is connected to the output of the third adder-subtractor, the third input of the decoder is connected to the output of the subtractor, the bit outputs of the binary counter are connected to an equalizer by their inputs of the first, second and third switches, the third and fourth inputs of the second element 2-2И-OR are connected to the control inputs of the device, and the bit outputs of the fourth shift register are connected to the information input of the third switch, the output of which is connected to the input of the delay element AND information input of the seventh switch, the output of which is connected to the first input of the fourth sundmator operand

a subtractor, the output of which is connected to the first input (| x: 1 memory of the sixth switch and the first input of the operand of the reader; the second input of the operand is connected to the low-order output of the fifth shift register and its information input; the output of the sixth switch is connected to the information input of the fourth the shift register, the output of the lower bit of which is connected to the second information input of the sixth switch and the second input of the operand of the fourth adder-subtractor, the second information input of the seventh comm the first element is connected to the output of the delay element; the outputs of the first and second switches are connected respectively to the first information inputs of the fourth and fifth switches and the second information inputs of the fourth and fifth switches; the outputs of the fourth and fifth switches are connected to the second inputs of operands of the first and second adders, respectively subtractors.

The invention relates to computing and is intended to build specialized digital computers on its basis. Arithmetic devices known to work with information, presented in the form of vectors, are designed to solve problems containing a large number of trigonometric functions 01. The closest to the proposed technical essence is device 2, which uses the Wolder, Woo, U algorithm; 2- ;; ; x, h, X. -; y; 1 (1) QU, ® -; "s; . J. where sign 0; to calculate the values of y k (xj cos) t f 2 X k (to cos kp - y sin If) J or - sign for the relations R - + y; a arctg .y / x, where X; , Xj - vector coordinates rotated by angle Qi / i; aCi arctg constants (i 2,3, ... n). A disadvantage of the known devices is the change in the scale of the representation of the variables (coefficient k 1), which makes programming more complicated. The aim of the invention is to expand the functionality of the device by calculating an expression of the form A /. , у у (у cos If + x,); X COBS - y sin If) J R f YQ arctg y / X. At Z k, the device allows to multiply the coordinates by the number A with the compensation of the scale, and at A k - Z - division of the vector coordinates by the constant Z (Z A). The goal is achieved by those. that the computing device containing the first, second and third shift registers, the first, second and third adders-subtractors, the first and second switches, and the outputs of the lower bits of the first, second and third shift registers are connected to the first inputs of operands, respectively the first, second and third adders-subtractors, the outputs of the first, second and third adders-subtractors are connected to the information inputs of the first, second and third shift registers, respectively, the bit outputs of the first and The first shift registers are connected to the inputs of the first and second switches, respectively, the second input of the operands of the third adder-subtractor is connected to the information input of the device, the output of the first adder-subtraction TBL is connected to the information output of the device, and a quarter and fifth fifth shift registers and switches are added from the third to the seventh, the fourth adder, the subtractor, the delay element and the control unit containing the decoder, the first, second and third triggers, the clock generator, the binary counter, the first and second elements 2-2 and-OR, and the EXCLUSIVE OR element, whose output is connected to the zero input of the first trigger, whose single input is connected to the output of the clock generator and the clock input of the binary counter, the counting input of which is connected to the single output of the first Trigger, the synchronization input of the second trigger and the first input of the first element 2-2 and-OR, the second input of which is connected to the output of the second element 2-2I-SH, the first input of which is connected to the first output of the decoder, the second output to the second is connected to the second input of the second element 2-2И-И11И, the zero output of the first trigger is connected to the third input of the first, second element 2r2I-OR and to the synchronizing input of the third trigger, the single input of which is connected to the third output of the decoder and to the single input of the second trigger whose single output is connected to the first input of the EXCLUSIVE OR element, the second input of which is connected to the single output of the third trigger and to the fourth input of the first element 2-2И-OR, and the first single output of the first trigger is connected with the control inputs of the fourth, fifth, sixth and seventh switches, the output of the first element 2-2И-OR is connected to the control inputs of the first, second and third adder-subtractors, the unit output of the third trigger is connected to the control input of the fourth adder-subtractor, the first input of the decoder is connected to the output of the second adder-subtractor, the second input of the decoder is connected to the output of the third adder-subtractor, the third input of the decoder is connected to the output of the subtractor, the bit outputs of the binary counter are connected S with control inputs of the first, second and third switchboards, the third and fourth inputs of the second element 2-2И-OR are connected to the control inputs of the device, and the bit outputs of the fourth shift register are connected to the information input of the third switch, the output of which is connected to the input of the element delay and the first information input of the seventh switch, the output of which is connected to the first input of the operand of the fourth adder-subtractor, the output of which is connected to the first information input of the sixth switch The ora and the first input of the subtractor's operand, the second input of the operand of which is connected to the low-voltage output of the fifth shift register and its information input, the output of the sixth switch is connected to the information input of the fourth shift register, the low-voltage output of which is connected to the second information input of the sixth switch and the second input of the operand of the fourth adder-subtractor, the second information input of the seventh switch is connected to the output of the delay element, the outputs of the first and second switches; ineny respectively to a first input of the fourth information in E th, the fifth switch and the second data inputs of the fourth and fifth switches, the outputs of the quat and fifth switches is connected to the second inputs of operands respectively governmental first and second adder subtractors, FIG. 1 is a block diagram of the computing device of FIG. 2 shows a structural scheme of the control unit; in fig. 3 - device operation algorithm. The device (Fig. O- contains the first to the fifth shift. Registers 1 - 5, the first to the AFTER comm mutators 6 - 12, the first to the fourth adders-subtractors 13 - 16, the subtractor 17, the delay element 18, the information input 19, the outputs and inputs 20 - 25 of the control unit, the control unit 26. The control unit (Fig. 2) contains the decoder 27, the first, second and third triggers 28-30, the first and second elements 2-2-OR 31 and 32, the element EXCLUSIVE OR 33, the clock generator 34 and the binary counter 35. The operation of the device can be described by the iteration algorithm x - - V if. 2 - Y 1, y, “- + g Y - x ,, 2; G; -f;;; -A; sign (A -);; LnpH; 0 where sip; n Qj for calculations (3) and j sign y - for calculations (4), For each iteration, two computation steps are performed. At the first step (rotation mode), relations (5) are implemented, and at step; the thore step (scaling mode), relations (6), which describe a change in the scale of the vector coordinates with checking the convergence of the iterative process ( equality check 2; ) When calculating relation (3), the device operates as follows. Current values of x, y, and angle Q; stored in registers 1–3, respectively, the current value of the divider is stored in register 4, and multiplier A is in register 5. From the beginning of the next iteration, switches 6–8 connect their inputs to the outputs of the corresponding registers, 4T (VHa outputs of switches 6 and 7, when the information in the registers is shifted, operands shifted by (i - 2) bits appear, and switch 8 is shifted by, (1 + 2) bits. At the output of delay element 18, the value Z appears, shifted by (i + 1) bits. The control unit generates signals according to the algorithm shown in FIG. 3. In the mode rotational output to the control unit output 21 is given a signal by which switches 9, 10, 12 connect the inputs of switches 6 to 8 with the inputs of adders 14,13, 16 respectively, switch 11 connects the output of register 4 with its input. 20 and 22 signals are sent, and F, A value is applied to input 19. The device implements the calculations (5), and, at outputs of adders-subtractors 13-16, the values,, y, S; +, 17 value (A - Z, - H (Z 2), which, together with the value 0, +) from the output of the subtractor 15 is served with the inputs 25 and 24 of the control unit to determine the operators; and correspondingly. The i i fi values are written to their registers. Operators fl and 2 are compared in the control unit, and if they are equal in the scaling mode, calculations (6) are implemented. In this case, the output of the control unit 26 is given a signal by which the switches 9, 10, 12 connect the outputs of the switches 6 and 7 and the delay element 18 to the inputs

totalizers-subtractors 14, 13, 16, respectively, and switch 11 connects the output of totalizer-1 reader to register A, input 19 is closed. At outputs 20 and 22 of the control unit, the value of the operator f- and the outputs of totalizers 13 - 16 are x,, 9 ,,, t which are written into the corresponding registers. From the output of the calculator 17, the difference (A-2) is fed through the input 25 to the control unit 26 to generate a signal ui. If there is no equality 1, the scaling mode is not executed. The iterations are repeated to a predetermined number. In step (4), the arithmetic unit operates in a similar way with the difference that the value of T is obtained as a function of the sign of the y coordinate, whose value is taken to the control unit at input 23. To control the switches 6 to 8, the signal corresponding to the number is removed from the output of the control unit iterations i.

After all the vector rotation operations have been performed, the coordinate values are multiplied by the number A or divided by Z without the addition of an extension of k.

To form a signal in the rotation mode, the inputs 23 and 24 of the decoder 27 of the sign of the operand (DC) are given the values of y, - and 0, respectively. Depending on whether the operation is performed (3) or (4) from the output of the logical circuit, the signal corresponding to the sign 6 (or, y), in the control unit, the trigger 28 sets the device operation mode: rotation - to the output 21 logical unit and scaling - to output 21 is logical zero. Trigger 29 produces signal L according to the sign of the operand from output 25 in rotation mode, and trigger 30 - signal in scaling mode. These signals come from the logical equivalence circuit, and if they are equal, trigger 28 sets scaling mode. Generator G serves to pulse the frequency of the calculation steps. These pulses are recalculated by a counter 35, which outputs the code of the iteration number. The signals for the initial setup of the block are not shown

The effectiveness of the invention is to expand the functionality of the device. In addition, absolute convergence of computations is provided over the entire variable variation range and programming of tasks is simplified, since there is no need to coordinate the scale of the operands in different parts of the program.

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Claims (1)

A COMPUTER DEVICE comprising first, second and third shift registers, first, second and third adders-calculators, first and second switches, the outputs of the least significant bits of the first, second and third shift registers being connected to the first inputs of the operands of the first, second and third adders, respectively subtractors, the outputs of the first, second and third adders-subtractors are connected to the information inputs of the first, second and third shift registers, bit outputs of the first and second. gaming registers are connected to the inputs of the first and second switches, the second input of the operands of the third adder-subtractor is connected to the information input of the device, the output of the first adder-subtractor is connected to the information output of the device, characterized in that., in order to expand the functional capabilities of the device by multiplying and dividing the coordinates of the vector by a constant, the device contains the fourth and fifth shift registers, switches from third to seventh, the fourth adder-subtractor, subtract l, a delay element and a control unit containing a decoder, first, second and third triggers, a clock pulse generator, a binary counter, the first and second elements 2-2I-OR, and an EXCLUSIVE OR element, the output of which is connected by the zero input of the first trigger, single the input of which is connected to the output of the clock generator and the clock input of the binary counter, the counting input of which is connected to the single output of the first trigger, the clock input of the second trigger and the first input of the first 2-2I-OR element, the second input of which horn is connected to the output of the second element 2-2I-OR, the first input of which is connected to the first output of the decoder, the second output of which is connected to the second input of the second element 2-2I-IPI, the zero output of the first trigger is connected to the third input of the first element 2-2I- OR with the synchronizing 'input of the third trigger, the single input of which is connected, with the third output of the decoder and with the single input of the second trigger, the single output of which is connected to the first input of the EXCLUSIVE OR element, the second input of which is connected to the single output the third trigger and the fourth input of the first 2-2I-OR element, the first single output of the first trigger connected to the control inputs of the fourth, fifth, sixth and seventh switches, the output of the first 2-2I-OR element connected to the control inputs of the first, second and third adders-subtractors, unit. the personal output of the third trigger is connected to the control input of the fourth adder-subtracter, the first input of the decoder is connected to the output of the second adder-subtracter, the second input of the decoder is connected to the output of the third adder-subtracter, the third input of the decoder is connected to the output of the subtractor, the bit outputs of the binary counter are connected to the control the inputs of the first, second and third switches, the third and fourth inputs of the second element 2-2I-OR connected to the control inputs of the device, and the bit outputs of the fourth the shift register is connected to the information input of the third switch, the output of which is connected to the input of the delay element And the first information input of the seventh switch, the output of which is connected to the first input of the operand of the fourth adder * * subtractor, the output of which is connected to the first information input of the sixth switch and the first input of the operand A reader, the second input of the operand of which is connected to the low-order output of the fifth shift register and its information input, the output of the sixth switch is connected the information input of the fourth shift register, the low-order output of which is connected to the second information input of the sixth switch and the second input of the operand of the fourth adder-subtractor, the second information input of the seventh switch is connected to the output of the delay element, the outputs of the first and second switches are connected respectively to the first information inputs of the fourth, fifth switches and second information inputs of the fourth and fifth switches, outputs of the fourth and fifth switches soy dinens with the second inputs of the operands, respectively, of the first and second adders - subtractors.