SU1166124A1 - Device for interfacing in multiterminal computer system - Google Patents

Abstract

1. A DEVICE FOR PAIRING IN A MULTI-TERM COMPUTER SYSTEM containing a communication unit with a digital computer, a terminal counter, a channel counter, a control unit, a switch, two sets of AND elements and a block of SHS elements, the first output of the control unit being connected to the write input of the channel counter , the output group of which is connected to the first group of inputs of the control unit and the first group of address inputs of the switch, the second group of address inputs of which is connected to the output group of the terminal counter and to the second a group of inputs of the control unit, the second output of which is connected to the first synchronized input of the communication unit with a digital computer, the group of information inputs of which are connected to the corresponding group of outputs of the block of OR elements, the first and second groups of inputs of which are connected to the groups of outputs of the first and second block of elements AND, respectively , the first group of inputs of the first block of elements And is connected to the first group of information outputs of the switch, with the corresponding outputs of the first group of information the switch outputs are connected to the information inputs of the channel counter, the first group of inputs of the second block of elements I is connected to the second group of information outputs of the switch, the second groups of inputs of the first and second blocks of elements And are connected to the first and second groups of outputs of the control block, respectively, the third output of which is connected to the counting the counting input of the terminal, the fourth output of the control unit (L is connected to the second synchronous input of the communication unit with a digital computer, characterized in that povvieni operating speed of information exchange with a term; A block of buffer: memory, a group of communication blocks with terminals and an I element are entered into it, the counting input of the terminal counter is connected to the first input of the I element, the output of which is connected to the reset input of the terminal counter, and the second input to the output Requiring an exchange of a communication unit with a digital computer and with a recording input of a buffer memory block, the read input of which is connected to the output of the exchange end of a communication unit with a digital computer, the group of information outputs of which is connected to a group of information in moves of the buffer memory block, the group of information outputs of which is connected to the first group of information inputs of the switch, the first control

Description

the input of which is connected to the output of the exchange request of the buffer memory block, the output of the exchange end of which is connected to the second control input of the switch, the output of the exchange request of which is connected to the first input of the control unit, the second and third inputs of which are connected to the first and second outputs of the exchange end of the switch, respectively The second output of the control unit is connected to the synchronous input of the block of buffer memory and to the first synchronized inputs of communication units with the terminals of the group, the second synchronized inputs of which are connected to the fourth output of the unit control, groups of information inputs of communication blocks with terminals of the group are connected to corresponding groups of outputs of the block of elements OR, outputs of the demand for exchange of communication blocks with terminals of the group are connected to the first group of control inputs of the switch, the second group of control inputs of which are connected to outputs of the end of exchange of blocks communication with terminals of the group, groups of information outputs of which are connected to the second group of information inputs of the switch, and the control unit contains two decoders, a trigger, two the OR element, the AND element, the master oscillator, the frequency divider, wherein the input groups of the first and second decoders form the first and second groups of inputs of the control unit, respectively, the output groups of the first and second decoders form the first and second groups of outputs of the control unit, respectively the outputs of the first decoder is also connected to a group of inputs of the first OR element, the output of which is the first output of the control unit, the single trigger input is the first input of the control unit, the first and The second inputs of the second element OR are the second and third inputs of the control unit, the code of the frequency divider is the second output of the control unit, the output of the And element is the third output of the control unit, the first output of the master oscillator is connected to the first input of the And element and is the fourth output of the unit control, the output of the second element OR is connected to the zero input of the trigger, the unit output of which is co6124

dinene with permitting inputs of the first and second decoders, zero output of the trigger is connected to the second input of the element And, the second output of the master oscillator is connected to the input of the frequency divider.

2. The device according to claim 1, wherein the buffer memory block contains two delay elements, a write address counter, a read address counter, a comparison circuit, a multiplexer, a trigger, two OR elements, four AND elements, and a random access memory. , the group of information inputs of the RAM forms a group of information inputs of the buffer memory block, a group of outputs of the RAM forms a group of information outputs of the block of buffer memory, the first input of the first element I is connected to, the recording input of the RAM, from the first The first input of the first element OR is the write input of the buffer memory block, the first input of the second And element is connected to the first input of the third And element, and is the read input of the buffer memory block, the input of the first delay element is connected to the first inputs of the fourth And element and the second the OR element and is the synchronous input of the buffer memory block, the outputs of the first OR element and the third AND element are outputs of the exchange requirement and the end of the exchange of the buffer memory block, respectively, the output of the first delay element is connected to the secondary the first input of the first element, the output of which is connected to the counting input of the write address counter, the output group of which is connected to the first input groups of the comparison circuit and the multiplexer, the output group of which is connected to the address input of the main memory whose input is connected to the second input of the first element OR , with a single trigger output, with a control input of a multiplexer and with a second input of the fourth AND element, the output of which is connected to the second input of the second OR element and to the input of the second delay element, stroke which is connected to the counting input of the read address counter group whose output is connected to the second group of inputs of the multiplexer and comparing circuit, whose output is connected

with the second input of the second element And with the zero input of the trigger, the zero output of which is connected to the second of the third element And, the single input of the trigger is connected to the output of the second element And, the output of the second element OR is connected to the synchronizing input memory.

The invention relates to automation and computing and can, in particular, be used in workstations for processing alphanumeric and graphic information. A device for exchanging information between a computer and a computer and input devices and a device is known, comprising an exchange hub, including an exchange processor, an exchange control node, an exchange register, a control signal register, a computer interface unit, a switching unit including a group amplifiers-forms of modules, M-groups of elements And, M-nodes address decoding, interface blocks with input devices and interface blocks with flash devices lj, The specified device has a low speed, large hardware The costs and complexity are the closest to the technical essence of the invention is a device for interfacing a digital computer (DVM) with a video terminal, containing a communication unit with a DVR, a control unit, a switch, channel and terminal counters, two units of elements - AND , signal level matching unit and delay element. The known device has a low IMM speed and requires significant computer time for communicating with electromechanical terminals, having low speed, does not provide for information exchange between terminals without interfering with digital computer and connecting more than two terminals. The purpose of the invention is to increase the speed of information exchange with the terminals. The goal is achieved by the fact that a device for interfacing in a multi-terminal computing system, a topic containing a communication unit with a digital computer, a terminal counter, a channel counter, a control unit, a switch, two blocks of AND elements and a block of OR elements, the first output of the block control unit is connected to the write input of the channel counter, the output group of which is connected to the first group of inputs of the control unit and the first group of address inputs of the switch, the second group of address inputs of which is connected to the output group of the terminal counter and c the second group of inputs of the control unit, the second output of which is connected to the first synchronous input of the communication unit with a digital computer, the group of information inputs of which are connected to the corresponding group of outputs of the OR block, the first and second groups of inputs of which are connected to the output groups of the first and second block of elements AND, respectively, the first group of inputs of the first block of elements I is connected to the first group of information outputs of the switch, while the corresponding outputs of the first group of information outputs of the switch are connected The first group of inputs of the second block of elements I is connected to the second group of information outputs of the switch, the second groups of inputs of the first and second blocks of elements I are connected to the first and second groups of outputs of the control unit, respectively, the third output of which is connected to the counter input of the counter. the terminal, the fourth output of the control unit is connected to the second synchronized input of the block, communication with the digital computer, a block of buffer memory, a group of communication blocks with the terminals and an element I are inserted, the terminal counter stroke is connected to the first input of the element I, the code of which is connected to the reset input of the terminal counter, and the second input to the output of the exchange request of the communication unit with the digital computer and the recording input of the buffer memory block, the read input of which is connected to the output of the exchange end of the block connection C of a digital computer whose information output group is connected to a group of information inputs of a buffer memory unit, a group of information outputs of which is connected to the first group of information inputs of a switch, the first control input of which is connected There is no output from the exchange request of the buffer storage unit, the end of exchange of which is connected to the switch's control input, the output of the exchange of which is connected to the first input of the control unit, the second and third inputs of which are connected to the first and second outputs of the switch exchange end, respectively, The second output of the control unit is connected with the synchronous input of the buffer memory unit and with the first synchronized inputs of the communication units with the terminals of the group, the second synchronized clock of which is connected to the fourth output of the control unit, group The information inputs of the communication units with the terminals of the group are connected to the corresponding output groups of the OR block; the outputs of the exchange of communication blocks with the terminals of the group are connected to the first group of control inputs of the switch, the second group of control inputs of the exchange communication units with terminals of the group, groups of information outputs of which are connected to the second group of information inputs of the switch. The control unit contains two decoders, a trigger, two elements OR an AND element, a master oscillator, a frequency divider, and the groups of inputs of the first and second decoders form the first and second groups of inputs of the control unit, respectively, the groups of outputs of the first and second decoders form the first and second groups of outputs the control unit, respectively, and the group of outputs of the first decoder is also connected to the group of inputs of the first element SH, the output of which is the first output of the control unit, the single input trigger This is the first input of the control unit, the first and second inputs of the second element OR are the second. And the third inputs of the control unit, the output of the frequency divider is the second output of the control unit, the output of the AND element is the third output of the control unit, the first output is set; 1; connected to the first input of the AND element and is the fourth output of the control unit; the output of the second OR element is connected to the zero input of the trigger, the single output of which is connected to the enable inputs of the first and second decoders, zero second output latch coupled to .vtorym input AND gate, the second output of the master oscillator is coupled to the input of the frequency divider. The buffer memory block contains two delay elements, a write address counter, a read address counter, a comparison circuit, a multiplexer, a trigger, two OR elements, four AND elements, and a random access memory, and the group of information inputs of the main memory form a group of information inputs of the buffer block. memory, the RAM EXIT group forms a group of information outputs of the buffer memory block, the first input of the first element I is connected to the input of the operational memory record with the first input of the first OR element and is input the recording house of the buffer memory block, the first input of the second element AND is connected to the first input of the third element AND is the read input of the buffer memory block, the input of the first delay element is connected to the first inputs of the fourth AND element and the second element SH and is the synchronous input the buffer memory, the outputs of the first OR element and the third AND element are outputs of the exchange requirement and the end of the exchange of the buffer memory block, respectively, the output of the first delay element is connected to the second input of the first AND element, the output of which connected to the counting input of the write address counter, the output group of which is connected to the first input groups of the comparison circuit and multiplexer, the output group of which is connected to the address input of the main memory, the reading input of which is connected to the second input of the first OR element, to the single output of the trigger, the main input of the multiplexer and the second is the input of the fourth And element, the output of which is connected to the second input of the second OR element and to the input of the second delay element, the output of which is connected to the counting input A reading address, the output group of which is connected to the second multiplexer and comparison circuit input groups, the output of which is connected to the second input of the second element And to the zero input of the trigger, the zero output of which is connected to the second input of the third element And, the single input of the trigger is connected to the output the second element AND, the output of the second element OR is connected to the synchronizing input of the RAM. FIG. Figure 1 shows the structural scheme of the proposed device for conjugation; in fig. 2 - structurally functional scheme of the buffer memory block; in fig. 3 - switch block diagram; Fig. 4 is a functional block diagram of the control unit; in fig. 5 is a diagram of the block of elements I; in fig. 6 is a block diagram of the elements of IS. The device for interfacing contains (Fig. 1) channel 1 of communication with a digital computer, channel 2 of communication with the terminal, group 3 of channel 2 of communication with terminals, i block 4 of communication with digital computer, group 5 of blocks 6 of communication with terminals, element 7 AND, terminal 8 counter, block 9 of buffer memory, switch 10, counter 11, (control block 12, first 13 and second 14 blocks of AND elements, block 15 OR of elements. Block 9 of the buffer memory contains (Fig. 2 a) the first 16 and second 17 delay elements, the second element 18 AND, the first element 19 AND, the fourth element 20 OR, the write address counter 21, the read address counter 22, the circuit 23 compared and, the second element 24 And, the trigger 25, multiplexer 26, the first element 27 OR, the third element 28 And, the operational memory 29. Switch 10 contains (fig.Z) first 30, second 31 and third 32 multiplexers, first 33 and second 34 groups of multiplexers 35. The control unit 12 contains (FIG the second element 36 OR, the trigger 37, the second 38 and the first 39 decipher) the master oscillator 40, the first element 41 OR, the element 42 AND, the frequency divider 43. A device for interfacing is connected to a digital computer via communication channel 1, and a group of terminals via channels 2. As part of a group of terminals | There is at least one video terminal (for example, EU-7927 from the display complex EU-7920 or EU-7905), one or more tape drives (for example, EU-9004, EU-9009 and EU-9051), electromechanical output terminals (for example, alphanumeric). printers EU-7032, EU-7036) and others. The digital-communications unit 4 and the terminal-communication units 6 are designed to convert information received in a serial code to the output of a device and a block into a parallel code issued to an M-bit group of information outputs for converting information into a parallel code received on an M-bit group of informational, inputs, to a serial code issued to the input - output, decoding of signals (commands) Exchange requirement, End of the exchange and issuing them to the corresponding outputs. Blocks 4 and 6 are identical and are made according to well-known schemes and technical descriptions of peripheral devices of the EC-1035, EC-1045 computer and the EC-7920, EU-7970 display complexes. The terminal counter 8 forms, at its outputs, a K-bit code of the terminal number in accordance with the number of signals received at its input. The buffer memory unit 9 (Fig. 2) is intended to coordinate the exchange of information between a high-speed digital computer and low-speed electromechanical terminals. The information from block 4 of communication with the digital computer goes in parallel code to the M-bit group of information inputs of block 9 and is stored in the operational memory (SP) 29 when there is a signal at the first input of block 9 Exchange request received at the input Record SP 29 At the same time, this signal through the first element 27 IZH arrives at the output 1 of block 9 and permits the passage through the first element 19 of the sync signals from the synchronous input of block 9 delayed by the first 7 delay elements 16 to the counting input of the write address counter 21. These sync signals are also fed through the second element 18 And to the input of the synchronization OP 100. The first delay element 16 ensures that the write address counter 21 is transferred to a new state only after the termination of the signal at the input of the OP synchronization 29. The T-bit code of the write address from the outputs the counter 21 arrives at the T-bit first groups of inputs of the comparison circuit 23 and the inputs of the multiplexer 26, the control input of which receives a signal. About from the single output of the trigger 25, allowing it to issue a T-bit address of the write address to the OC 29, this prevents the passage of signals to the input of Read OP 29. The trigger 25 is set to the state O, both when the device is initially turned on and when comparing the write address and read address codes from counters 21 and 22. Thus, information of the digital computer is stored in the OP 29 of the buffer block 9: memory, after which the communication module 4 of the secondary computer outputs to its input 2 a signal of the exchange end, which , acting through the open second element 24 And (sig The comparison of the output of the circuit 23 is absent), sets the trigger 25 to state 1 and does not pass to the output 2 of block 9, since there is no permit signal at the second input of the third element 28I. At the same time, the signal Exchange is demanded at the input 1 of block 9, thereby, the operation of the OP 29 in the recording mode is stopped (the delayed clock signal is prevented from passing through the first element 19 I). The reading process is similar to the writing process and is carried out on the synchro signals received at input 4 of block 9. When a signal is removed, the exchange request at input 1 of block 9 at its output 1 signal the exchange request is formed by trigger 25, from a single output of which 1 signal goes to input 1 through the first element 27 ШШ. The reading process continues until comparing the write address codes (T-bit of the first group of inputs of comparison circuit 23) and reading 4 (T-of the second group of inputs of comparison circuit 23). In this case, the comparison signal sets the trigger 25 to the state O and thus the signal is removed. The exchange request at output 1 of block 9 is allowed and the signal is allowed to pass. The exchange end to output 2 of block 9. Switch 10 (Fig. 3) is intended for selection and electronic switching information and control signals (commands) of communication unit 6 with terminals and buffer storage unit 9 (information of communication unit 4 with a digital computer). The first multiplexer 30 commutes the exchange request signals, the second 31 signals. The end of the exchange from the terminals - initiators of information exchange Third 32 - End of signals caused by the exchange to exchange information terminal or a digital computer. The first group 33 of multiplexers 35 provides a selection of information from information inputs of blocks 6 and 9, initiators of information exchange, and outputs it to an M-bit first group of information outputs of switch 10. The second group 34 of multiplexers 35 provides a selection of information from information outputs of blocks 6 and 9, called on the exchange of information, and gives it to the M-bit second group of information outputs of the switch 10. (n ± 1) -bit groups of the inputs of multiplexers 35 are connected to the M-bit fourth group of information inputs Od and M-bit third group of information inputs of switch 10, and on ke M M-bit groups multiplexers 35 of the first 33 and second 24 groups are served ke bits of M-bit groups in the following order: on the first input of k-ro multiplexer 35 k-th bit of the first group of fourth information inputs of the switch 10, to the second input of the k-ro multiplexer 35 k-th bit of the second group, to the L-input of the k-ro multiplexer 35 k-th bit of the l-th group, to (L + 1) is the input of the k-ro multiplexer 35 of the kth bit of the M-bit third group of information inputs. (L + 1) -sized groups of inputs of the first multiplexer 30 are connected to the A-first inputs and input 2 of the switch 10, the second 31 and the third 32

9, 1

multiplexers - with A-second inputs and input 2 of switch 10, with input 1.1 of the first group of control inputs of switch 10 connected to input 1 of multiplexer 30, input 1.2 to 2 input of multiplexer 30, input 1 k-th to kM input of multiplexer 30 , input 1. L- with l-INPUT of multiplexer 30, input 1 - with () input of multiplexer 30, input 2.1 of the second group of control inputs of switch 10 is connected to inputs 1 of multiplexer 31 and 32, input 2.2 with 2 inputs of multiplexers 31 and 32 , input 2.k - with K-inputs of multiplexers 31 and 32, input 2.l - with L-inputs of multiplexers 31 and 32, input 2 s (l + 1) multiplexer inputs 31 and 32.

The K-bit control groups of the multiplexers 30, 31, and 35 of group 33 are connected to the K-bit first group of information inputs of the switch 10, respectively, and the multiplexers 32 and 35 of the group 34 are connected to the K-bit second group of information inputs of the switch 10, respectively.

Channel counter 11 is used for storing the number of the K-bit switch’s 10 K-bit code number coming from the first group of outputs for the exchange of the terminal (channel) via clock signals from the first output of the control unit 12

The control unit 12 (Fig. 4) is designed to generate sync signals clocking the operation of the device, control signals in accordance with the binary codes of the addresses of the initiators of the exchange and the terminals called to exchange information.

When the device is turned on, the trigger .37 of block 12 is set to state O regardless of the presence of signals at inputs 2 and 3 of block 12, the exchange end, and thereby allows passage through the element 42 to the output 3 of block 12 of the clock signals of the generator 40. input 1 of signal block 12, the exchange request trigger 37 is set to state 1, prohibits the generation of sync signals at output 3 of block 12, and enables the decoding of the K-bit address codes of terminals initiating the exchange and ter410

The minals signaled for the exchange of information by decoders 38 and 30, respectively, whose outputs are the second and first information outputs of the block, respectively.

The outputs of the decoder 39 are also assigned to a group of elements 41 OR to generate a counter control signal 11 of the channel at the output 1 of unit 12 after each operation of the decoder.

Since the exchange of information between the terminals and the digital computer occurs in M-bit words, therefore, to ensure the operation of blocks 4, 6 and 9, the clock signal frequency () at the output of divider 43 (output 2 of control block 12) is associated with the frequency of pulses of the master oscillator 40 (ffg a) the following ratio

i

gene

Ael- W

The first block 13 of the elements And is designed to receive and switch on (A + 1) M-bit groups of its outputs (to (.) Direction in accordance with the address code of the terminal or digital computer called to exchange information received at (+1) - The block group of the second inputs of the block) information of the terminal or digital computer - initiators of the exchange coming from the switch 10, ia M-bit group of the first inputs of the block 13,

The second block 14 of elements And is designed to receive and switch on (A - "- 1) M-bit groups of its outputs (in (+1) direction in accordance with the address code of the terminal or CVM - initiators of the exchange received on (l + 1 ) - the bit group of the second inputs of the block) the infromation of the terminals or digital computers that are sent for exchange, coming from the switch 10 to the M-bit group of the first inputs of the block 14.

Blocks 13 and 14 are identical and contain (Fig. 5) by (l + 1) -groups 44 elements And from M-elements 45 And in each group.

The 1st bit of the M-bit group of the first inputs of block 13 (14) is connected to the inputs 1 of the first elements 45 And each of the (l + 1) groups 44, the k-th bit of the inputs 1 kx elements 45 And, M- zd d - with inputs 1 Mx of elements 45 And 1 st discharge (l-t-1) -d discharge of the group 11 1

The second inputs of the block 13 (14) are connected to the inputs 2 of all elements 45 of the first group of 44 elements I, the k-th bit - with the inputs 2 of all elements AND 45 of the lc-th group 44 elements And, (A 4-1) -and bit d - with the inputs of 2 all elements 45 And, (A + 1) - a group of 44 elements I.

Block 15 of the OR elements (Fig. 6) is intended for bit-wise information gathering from the outputs of blocks 13 and 14 of the elements AND, acting on (A + 1) M-bit groups of the first and second inputs of block 15, issuing it to (L + 1 ) M-bit group of outputs of block 15 and contains (+1) -groups of 46 elements from M-elements 47 OR. :

The device for interfacing provides five modes of information exchange: the first mode of recording information on the k-th terminal on the initiative of the digital computer, the second mode of recording from the digital computer on the k-th terminal on his initiative (demand), the third mode of reading information from the k-terminal , on the initiative of the digital computer, the fourth mode of reading the digital information center from the k-ro terminal on its initiative (demand), the fifth mode of information exchange between the 1st and 2nd terminals without the participation of the digital computer.

 In this case, the initiator of the exchange of information can be any terminal other than electromechanical (for example, alphanumeric printers).

The beginning of any of the listed operation modes is provided only when a signal is received from the digital computers or terminals of the initiators of information exchange. The requirement of exchange (its code via communication channels). In the absence of signals, the Requirement of exchange the interface device works as follows.

The terminal 8 counter, on the basis of the sync signals from the output 3 of the control unit 12, forms for the switch 10 and the unit 12 on its K-bits outputs the codes of the exchange initiator numbers, according to which the switch 10 provides switching. And the signal flow from the outputs requires the exchange of blocks 9 and 6 to input 1 of control unit 12, which analyzes the presence of a signal exchange request.

In the absence of an Exchange Requirement Signal from the exchange initiators, the operation cycle is repeated. In the presence of sig12

24

The exchange request block 12 fixes it and terminates the timing signal on the counting input of the counter 8 of the terminal, which stores the code of the exchange initiator, the signal whose exchange request is processed.

The priority of the CVM among the initiators of the exchange is provided by the Signal Requirement of the exchange from block 4, which, through element 7, resets the counter 8 to the state O, and at its output the code number 0-0 CVM is formed. .

In the first mode, recording information to the k-th terminal at the initiative of the digital computer, the device operates as follows.

On the Signal Requirement of the exchange of the communication unit 4 with the digital computer by the buffer memory unit 9, the same signal is generated, which through the switch 10 enters the control unit 12 where it is recorded. In this case, the subsequent survey of initiators of the exchange is terminated.

Simultaneously with the signal, the requirement to exchange a digital computer via block 4 is fulfilling. information c, the number code of the terminal to be called in block 9. After the end of the information output, a signal is generated. The end of the exchange, which is recorded in: block 9.

On a signal The end of the exchange, the buffer memory block 9 starts the autonomous exchange of the information received from the digital computer with the one called in accordance with the received number code for the exchange of the kth terminal. The number code is stored by the channel counter 11 over the sync signal of block 12 and is stored until the exchange of information between block 9 and the selected k-M terminal is completed. The information from block 9 goes through the switch 10 to the first inputs of the first block 13 of the elements I, the second inputs of which from the control block 12 receive the position codes of the numbers called on the exchange terminals. From the outputs of block 13, the information enters through block 15 OR to the information inputs of block 6 of the selected terminal.

When the output of information is completed at the speed of the terminal memory block called for exchange, the buffer memory block 9 generates a signal for the exchange end which permits subsequent polling of the initiators of the exchange.

Thus, the exchange of information of the digital computer with the kth terminal through the buffer memory of block 9 is ensured and the exchange time in this case depends only on the speed of the digital computer and does not depend on the low speed of information processing by electromechanical terminals.

In the second recording mode from the digital information center to the 1st terminal according to his 10th initiative (demand), the device works as follows.

The terminal initiating the exchange through the corresponding communication unit 6 sets the signal for the Exchange request 15, which from the output of the exchange request of the corresponding block 6 enters through the switch 10 to the control unit 12, where the further polling of the initiators of the exchange is recorded and blocked. 20 At the same time, at the information outputs of the corresponding block 6, the digital computer number code (O-O) is supplied, which is fed through the switch 10 to the counter 11 and then to the control unit 12 25.

Thus, the outputs of the U-ro of the communication unit 6 with the terminal are connected to the information inputs of the digital communication unit 4 with a single-time transmission of the required information signs, in accordance with which the digital drive generates the exchange request signal and outputs, through block 9, a buffer -. memory in the stated order for the 35th kth terminal - the initiator of the exchange of information with a digital computer required information.

In the third mode of reading information from the U-ro terminal initiated by the digital computer, the device operates in the following 40 ways.

Similarly to the first mode, the digital computer transmits through block 4 to block 9 the code of the number of the called terminal and the block of signals with the signs required for 45 steps of information, sets up the End of Exchange signal and goes to a decision. other information processing tasks. The block 9 of the buffer memory transmits command information to the currently called 50th terminal. Upon completion of the preparation of the requested information, this terminal issues a signal to request an exchange with a digital computer and starts outputting information to a digital computer, at the end of which 55 the terminal sets a signal to the end of exchange, and allows subsequent interrogation of initiators of the exchange.

The operation of the device in the fourth reading mode of digital information from the -th terminal, on its initiative, is similar to the second part of the operation of the device in the third reading mode of information from the k-ro terminal, initiated by the digital computer.

In the fifth mode of information exchange between k-M and m-th terminals without the participation of the digital computer, the device operates as follows. . ,

Upon receipt of the K-th channel 2 to the corresponding block 6 of communication with the terminal of information with codes, the exchange request and the number of the rst terminal to be connected, the block 6 generates a signal for its switch 10, the exchange request signal, and on the information outputs, the code of the called t go terminal.

. In accordance with this information, the switch 10 provides a sample of information from the information outputs of the t-th block 6 to its second group of information outputs and its output to the inputs 1 of the second block 14 elements I.

At the same time, the scraper code of the k-ro terminal, the exchange initiator, which is fed to the second groups of information inputs of the switch 10 1 of control unit 12, is recorded at the outputs of the counter 8 of the terminal.

In accordance with the incoming initiator code of the exchange, the switch 10 provides a sample of the information outputs of the k-ro of the communication unit 6 with the terminal to its first group of information outputs, passes it to the inputs 1 of the first block 13 of the I elements and the K-th bit code of the channel number counter 11, which remembers it and introduces the first group of information inputs of the switch 10 and the control unit 12.

Unit 12 control c. according to the codes of the k-ro and t-th terminal numbers, respectively, entering the second group of information inputs from the counter, the 3rd first group of information inputs from counter 11 forms, on the second and first groups of information outputs, positional co / tsl and k-ro terminals respectively.

These signals, arriving at the inputs 2 of the first 13 and second 14 blocks of AND elements, resolve through the block 15 elements OR information

15P

information outputs of the k-ro block 6 to the information inputs of the t-th block 6 and information outputs of the th-th block 6 to the information inputs of the k-ro block 6 of communication with the terminal.

Further exchange of information is carried out directly between the switched terminals under the control of the terminal initiating the exchange. Upon completion of the exchange of one of the terminals, the End of Exchange signal is output through the corresponding block 6, which, entering through the switch 10 to the control block 12, allows subsequent polling of the initiators of the exchange and exchange of information.

In comparison with the known device, the proposed device provides an increase in the speed of information exchange with the terminals, an increase in the speed of information exchange of the digital computer by addressing and writing information to the buffer memory unit, and not directly with low-speed electromechanical terminals, autonomous information exchange between the terminals without the participation of digital computers, which expands the functionality of solving the problems of processing and preparing information for the central mechanical surgery, the coordination of high-speed digital computers multispeed slowly operating terminals of different types of performance and administration by introducing a buffer unit pa16

mti, an increase in the number of terminals connected to a digital computer (there are only two in the known device).

Technical and economic efficiency is achieved due to saving of useful machine time spent on information exchange, increasing the efficiency of using computational tools, efficiency and quality of operators preparing information for processing on digital computers by creating automated workplaces on the basis of this device. interim media such as magnetic tape alphanumeric and graphic information, its control and editing offline without the fate of digital computers, input and view in digital computers with the ability to document, work with digital computers in an interactive mode.

The magnitude of this effect depends on the implementation of subscriber stations and complexes based on digital computers, in particular, on the number of computer centers equipped with these devices, and on the number of terminals connected to digital computers through the proposed device.

The use of this invention will reduce the loss of computer time and increase the efficiency of operating digital computers.

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Claims (2)

1. A device for interfacing in a multi-terminal computing system, comprising a communication unit with a digital computer, a terminal counter, a channel counter, a control unit, a switch, two blocks of AND elements and a block of OR elements, the first output of the control unit being connected to a recording counter input channel, the group of outputs of which is connected to the first group of inputs of the control unit and the first group of address inputs of the switch, the second group of address inputs of which is connected to the group of outputs of the terminal counter and the second group th inputs of the control unit, the second output of which is connected to the first sync input of the communication unit with a digital computer, the group of information inputs of which is connected to the corresponding group of outputs of the block of OR elements, the first and second groups of inputs of which are connected to the output groups of the first and second block of AND elements, respectively, the first group of inputs of the first block of AND elements is connected to the first group of information outputs of the switch, while the corresponding outputs of the first group of information outputs of the switch the torus is connected to the information inputs of the channel counter, the first group of inputs of the second block of elements And is connected to the second group of information outputs of the switch, the second group of inputs of the first and second blocks of elements And are connected to the first and second groups of outputs of the control unit, respectively, the third output of which is connected to the counting input counting terminal, the fourth output of the control unit is connected to the second clock input of the communication unit with a digital computer, characterized in that, in order to improve performance In order to exchange information with the terminals, a buffer block is entered into it- ·! memory, a group of communication blocks with the terminals and the And element, and the counting input of the terminal counter is connected to the first input of the And element, the output of which is connected to the reset input of the account (Л 1166) 24 hours of the terminal, and the second input - with the output of the requirement to exchange the communication unit with the digital computer and with the write input of the buffer memory unit, the read input of which is connected to the output of the end of the exchange of the communication unit with the digital computer, the group of information outputs of which are connected to the group information inputs of the buffer memory block, the group of information outputs of which is connected to the first group of information inputs of the switch, the first control input of which is connected to the output of the buffer block exchange request memory, the output of the end of the exchange of which is connected to the second control input of the switch, the output of the demand of the exchange of which is connected to the first input of the control unit, the second and third inputs of which are connected to the first and second outputs of the end of the exchange of the switch, respectively, the second output of the control unit is connected to the sync input of the buffer unit memory and with the first sync inputs of communication units with group terminals, the second sync inputs of which are connected to the fourth output of the control unit, the group of information inputs of communication units from the terminal the groups are connected to the corresponding groups of outputs of the block of OR elements, the outputs of the requirement for exchanging communication blocks with the group terminals are connected to the first group of control inputs of the switch, the second group of control inputs of which are connected to the outputs of the end of the exchange of communication blocks with the group terminals, the groups of information outputs of which are connected to the second group of information inputs of the switch, and the control unit contains two decoders, a trigger, two OR elements, an AND element, a master oscillator, a frequency divider, at m groups of inputs of the first and second decoders form the first and second groups of inputs of the control unit, respectively, groups of outputs of the first and second decoders form the first and second groups of outputs of the control unit, respectively, and the group of outputs of the first decoder is also connected to the group of inputs of the first OR element, the output of which is the first output of the control unit, a single input of the trigger is the first input of the control unit, the first and second inputs of the second element OR are the second and third inputs of the unit and the control, the output of the frequency divider is the second output of the control unit, the output of the And element is the third output of the control unit, the first output of the master oscillator is connected to the first input of the And element and is the fourth output of the control unit, the output of the second OR element is connected to the zero input of the trigger, single output which is connected to the enabling inputs of the first and second decoders, the zero output of the trigger is connected to the second input of the And element, the second output of the master oscillator is connected to the input of the frequency divider. 2. The device pop. ^ characterized in that the buffer memory unit contains two delay elements, a write address counter, a read address counter, a comparison circuit, a multiplexer, a trigger, two OR elements, four AND elements, and RAM, while the group of information inputs of the RAM forms a group of information inputs the buffer memory block, the group of RAM outputs forms a group of information outputs of the buffer memory block, the first input of the first element AND is connected to the input of the RAM record, with the first input of the first element that OR is the write input of the buffer memory block, the first input of the second AND element is connected to the first input of the third AND element and is the read input of the buffer memory block, the input of the first delay element is connected to the first inputs of the fourth AND element and the second OR element and is the sync input of the buffer block memory, the outputs of the first OR element and the third AND element are outputs of the exchange request and the end of the exchange of the buffer memory unit, respectively, the output of the first delay element is connected to the second input of the first element And, the output of which is connected to the counting input of the write address counter, the group of outputs of which is connected to the first groups of inputs of the comparison circuit and the multiplexer, the group of outputs of which is connected to the address inputs of RAM, the read input of which is connected to the second input of the first OR element, with a single trigger output , with the control input of the multiplexer and with the second input of the fourth AND element, the output of which is connected to the second input of the second OR element and with the input of the second delay element, the output of which is connected to th input read address counter group whose output is connected to the multiplexer inputs of the second group and the comparison circuit ^1, the output of which is connected ny trigger input connected to the output of the second AND gate, the output of the second OR gate is connected to the clock input of RAM. / with the second input of the second element And and with the zero input of the trigger, the zero output of which is connected to the second input of the third element And,