SU1160366A1 - Device for programmed control of winding equipment - Google Patents

Abstract

1. DEVICE FOR SOFTWARE EQUIPMENT MANAGEMENT, containing a comparator, a memory, an address counter and an address generation control unit, wherein the first information outputs of the memory unit are connected to the first inputs of the comparator, the output of which is connected to the first input of the address generation control unit, the second input of which connected to the operational output of the memory unit, and the first and second outputs of the address generation control unit are connected respectively to the counting and control inputs of the address counter, e onn; the output of the memory unit connected to the first address of the memory block, t, and h; And in order to increase the speed of the device, it contains a switch, the information input of which is the device input, and the output is connected to the second input of the comparator, a block of registers, a block of elements. Comrade OR, the first and second elements AND, the current address memory block, the start block, the pulse generator, the channel number counter and the synchronizer, whose input is connected to the output of the pulse generator, and from the trans. the sixth outputs of the synchronizer are connected respectively to the first input of the first element AND connected to the third input of the address generation control unit, the control input of the memory unit, the first input of the second element AND, the fourth input of the address formation control unit (L to the first control input the current address memory block and to the counting input of the channel number counter, the transfer output of which is connected to the input of the start block, the first output connected to the sync reset inputs oO5 of the nominator and canana counter numbers, and the second output is to the second input of the first element, whose output is connected to the second directors control of the current address memory block, whose information inputs are connected to the output of the address counter, information input connected via OR to the outputs of the memory block of current addresses and the interconnected second information output of the memory block and the information input of the register block, and the address inputs of the register block combined with the second addresses Traditional

Description

.one

the inputs of the memory block and the address B: co-amps & 1utator and the memory block of current addresses are connected to the information outputs of the channel number counter, the control input of the register block is connected to the output of the second And element, the second input of the memory block connected to the operational output, and the output of the block register is the device's input.

2, The device according to claim 1, that is, so that the block forming the address contains the elements OR, the third element AND,

60366

as well as the UNIVERSAL and BANNER elements, the first and second inputs of which are connected respectively by the mead and connected to the first and second inputs of the block, the first input of the third element AND connected to the third input of the BANNER element and a quarter input of the block, the second input - with the output of the EQUALITY element, and the output with the first output of the block, the third input and the second output of which are connected respectively to the first input and output of the OR element, the second input connected to the output of the BAN element.

- : , one

The invention relates to automation and computing, and is intended for use in software systems for controlling aggregates for the production of winding products.

A device for software control of winding equipment is known, comprising a successively connected pulse generator, a BANE element, an address counter and a memory unit, the first output of which is connected to one comparator input, the second input of which is the device input, and the comparator output is connected to the second input of the element. BAN, with the second output of the memory block being the output of the device C

The device provides cyclic program control of the winding equipment, but does not allow several programs to run in parallel, i.e. does not provide asynchronous mode of operation of individual groups of machine mechanisms.

. . . - ,. ,

Closest to the proposed

The invention is a device for software control of winding machines, comprising a comparator, a memory unit, an address counter and an addressing unit; the first information output of the memory unit is connected to one comparator input, the output of which is connected to the first

A descent of the address generation unit, the second input of which is connected to the operational output of the memory unit, and the two outputs of the address generation unit are connected respectively to the counting and control inputs of the address counter, its output connected to the first address input of the memory unit.

The device provides logical control over the operation cycle of one group of mechanisms of the winding machine and change of the operation cycle of the MHbiM program by C2.

A disadvantage of the known device is low speed, since it does not ensure the movement of the working bodies of each of the groups of equipment mechanisms according to an independent program, not dependent. on the states of the mechanisms of other groups.

The aim of the invention is to increase rapidly;

This goal is achieved in that a device for software control of winding equipment, comprising a comparator, a memory unit, an address counter and an address generation control unit, the first information outputs of the memory unit connected to the first inputs of the comparator whose output is connected to the first input of the formation control unit addresses, the second input of which is connected to the operational output of the memory block, and the first and the second outputs of the addressing control block are connected in a fine way to the counting and control yuschemu inputs of counter addresses, they svo- 5 output coupled to the first address input blrka memory with g-holding switch, whose data input is VZHUDOM ustrrystva and an output connected to the secondary. 10 to the comparator input, a register block, an OR block, the first and second AND blocks, an address memory block, a trigger block, a pulse refractor, a 15-channel counter and a synchronizer whose input is connected to the output of the pulse generator, and The synchronizer outputs are connected, respectively, to the connected & {20 each other, the first input of the first element K and the third input of the address formation control unit, which controls the INPUT of the memory unit, the first input of the second element, and even

The first control input of the current memory block and the counting input of the channel number counter are connected to the trigger input, the first output connected to the interconnected inputs

reset the synchronizer and the channel number counter, and the second output is 35 to the second input of the first element AND, the output of the control panel; 1to the second control block of the current address memory block, the information inputs are connected to the output of the address meter 40, information input of the PDR | connected via a block of IDN elements to the outputs of the memory block of current addresses and connected between the second contact information outputs 4S of the memory memory and information inputs of the access control register, combined with the second addresses the inputs of the memory block and the address inputs of the commutator and the memory block of the current addresses are connected to the information outputs of the channel number counter, which controls the input of the register block “with the output of the second element AND, the second,; 5 input connected to the operating output of the memory block and the regisPPQ block is the output of the device. .

In addition, the address shaping control unit contains IL elements, the third element AND, as well as the UNIVERSITY and BAN elements, the first and second inputs of which are connected to each other, respectively, and connected to the first and second emanations of the block, the first input of the third element1; the third input of the BANNER element and the fourth block of the block; the second input is from the output of the EQUALITY element, and the bypass - with the first output of the block, the third input and the second BbjkoA of which: are connected to the first input and output of the SH) element,; In the entrance is connected with the output of the element BAN.

Introduction to the device of the generator of pulses, synchronization, memory memory of the current addresses of the registrar block, AND, OR elements, H counter (Channels tepoB and start block, with a variety of links, each of the groups of equipment mechanisms independently program that is independent of the mechanisms of other groups.

Execution of the control of the formation of the address with the PERMITTED ELEMENTS, FORBIDDEN AND AND ISH with the appropriate links ensures the formation of addresses of the alternate commands for each of the device programs, i.e. a constant or variable sequence of oeration by the corresponding groups of mv enism winding equipment.

Fig. 1 shows a functional diagram of the device; Fig. 2 shows its operation j on the "HF Functional" diagram of the address generation control block in Fig. 4, the same, and the diagram of the operation of the synchronization in Fig. 5, is a functional diagram of the launch block.

The device contains a switch 1V memory comparator 2, 3, blrk 4 registers, address counter 5, address formation control block 6, block 7 of elements OR block 8 of memory of current addresses, generator of 9 pulses, synchronizer 10, second element II, 12 " channel numbers, run block 13, first element, And 14,

Block 6 controls the formation of the address contains the third element And 15, the element OR 16, the element EQUALITY 17 and the element BANE 18. The synchronizer 10 contains the counter 19, the decoder, the element MEMORY 21, the element OR 22. The start block 13 contains the trigger 23, the one-shot 24, the sensor 25 pulses of the initial installation and the element OR 26.

The device works as follows.

In block 3 of memory, implemented on the basis of integral programmable permanent memory devices, for each of the groups of winding equipment mechanisms, a corresponding work program is recorded. . Programs consist of a certain number of control words, which have zone III and have two types: commands for switching on and off mechanisms, commands for conditional transition.

The type of command is determined by the corresponding signs (G-or. O) listed in zone III of the memory. When reading the latter, a symptom occurs on the communication line L, which is the operational output of block 3.

The bits of the first information outputs (bus S) form the I memory zone, which is intended for storing combinations of states to which the mechanisms must arrive at zone II signals if the value of feature 1 is for storing possible transition condition codes, if the value of feature O.

The bits of the second information outputs (bus R) form the memory zone, which is designed to store a combination of control signals of the mechanisms in this step, if the value of feature 1, or address codes of the conditional jump, if the value of feature O. Addressing and reading the contents of cells all three zones are executed in parallel in accordance with the code arriving on bus P from the outputs of the counter 12 channel numbers (most significant bits of the address code) and on the T bus from the outputs of count 5 addresses (the lower bits of the address code). .

The number of controlled groups of winding equipment mechanisms is determined by the number of control channels. The control of the channels is divided in time by signals (FIG. 2) coming from the counter 5 12 of the channel numbers, while the synchronizer 10 generates the pulses necessary for transmitting and testing one command of the corresponding program.

0 The testing of the winding equipment program is carried out by alternately reading each of the control word memories from block 3 for each channel.

5 When working out a command, for example, the program of the first channel, 12 channel numbers transits via the bus P to the address inputs of switch 1., memory block 3, block 4 registers and

0 block 8 of the memory of current addresses code corresponding to the number of the first channel. ,

As a result, discrete sensors are connected to switch 1.

5 signals of the state of the mechanisms of the first channel, the code corresponding to the memory area where the program of operation of the mechanisms of the first channel is written to the second address inputs of the memory block 3, is selected in the memory block 8 of the current addresses the cell where the current address of the first control program is stored channel. I -:. . - Generator 9 pulses are fed to the first input of synchronizer 10 (line X), which absorbed a pulse at the first output (line A), coming through the first element 14 to the second control input of the current address memory block 8 as a signal Read block 8 and through the block 6 of the control of the formation of the address to the control input (line N)

 counter 5 of the address as a signal Record in block 5 (FIG. 2), while the current address of the control program of the first channel is derived from block 8 of the memory of the current a: address to

A ghost R and, through block 7 of the elements OR, is recorded in the counter 5 of the address; the latter, together with counter 12, selects by means of buses T and P the memory cells of block 3 corresponding to the current program address of the first channel. After the end of the first pulse, the synchronizer 10 issues a command. Reading unit 3, in its

7 . -

the second output (line B), which is fed to the control input of memory block 3. As a result, the control word is read, the bits of which appear on the operating, first and second information outputs of the block (link B, tires S and R respectively)

Further operation of the device depends on the type of the read word from block 3 8 of the result of comparison of codes with a comparator. When reading from the memory block 3, the words of the first type to the second input of the second item And 11, the permitting signal is given (sign 1 is present on the L link).

Simultaneously with the command on the second output, the synchronizer 10 impulses a pulse of shorter duration on. its third exit (line C). This pulse through the second element And 11 posyuyut on the control Input of the block 4 registers (line G) and writes the words from the second zone of block 3 memory in the register of the first channel of block 4 registers.

The signals from this register turn on the working bodies of the first group of mechanisms of the machine and their state changes, which are recorded by sensors of the state of the mechanisms of the first group.

The signals from the sensors through kommushtor 1 are sent to one of the inputs of comparator 2 (bus N), to the other input of which a combination of signals is received, recorded in the first call of the 3p block. At co-fall of Signals (working out a given teajpa program), the comparator 2 generates a signal 1, which is fed (communication line K) to the first control unit 6 of formation. address, otherwise the comparator 2 generates a signal O, Yipulse from the fourth output of the synchronizer 10, on the communication line D goes to the fourth input of the address formation control unit 6, at the second input (LINK line L) of which in this case there is a command indication enable and disable mechanisms.

Depending on the comparator's output signal, the number in the counter of the 5 address is increased by 1 or 60606.

without change. If at the output of the comparator, block 6 generates a pulse arriving via the communication line M at the counting input of the address counter 5 5, if at the output of the comparator this pulse is not generated.

When reading a word of the second type, a conditional transition command is implemented and a combination of conditions, in which quality can be used not only signals from sensors of mechanisms, but also controls from other devices. In this case, at the operational output: 5 (communication lines L) of memory block 3 there is a sign O, the second element 11 And is closed, blocking the passage of 1 in the synchronizer pulse 10 (communication line C) to control input 20 of block 4 registers. As in the nepacw case, the comparator 2 compares the sensor currents from sensors with a combination of signals received from the first information output of memory block 3. If they match, the comparator 2 outputs the signal 1, resulting in a 1-pulse forming the output of the synchronizer 10, iioiCTynaeT through block 6 and the line.

0 connection N to the control input of the counter 5 address. To the information input of the counter 5, the address goes through block 7 of the elements OR the address code, the transition from the second information

5 outputs of memory block 3. The transition to the specified step of the program of work for this channel.

If there is no match, the comparator 2 selects the signal O. Through block 6, the pulse generated at the fourth output of the synchronizer 10 passes to the counting input of the counter 5 of the address, which provides a transition to the next step of the program.

5 An impulse that forms at the fifth output of the synchronizer .10, regardless of the type of word, is sent via the communication lines E to the first control input of the block 13 of the memory of the current

0 addresses, the information input of which is supplied via the bus T with the contents of the counter of the 5 address, and the address input through the bus P with the code of the number of the first channel. The current program address from the address counter 5 is rewritten into memory block 8.

Shpulse from the sixth output of the synchronizer Yu translates counter 12

channel numbers to the state corresponding to the second channel, then the synchronizer 10 returns to the initial state,

The operation of the device with the control of 5 scientific research institutes with the second and tracking channels when developing all the program steps is similar to that described.

The address of the memory cell of block 3 is given by counter 12 (most significant bits of the address code) and counter 5 (least significant bits). The higher-order address codes determine the memory areas in which the programs of each winding equipment group are recorded. The lower bits are specific cells of the corresponding two memory areas in which the control words of these programs are recorded.

The low bits of the initial address code of the work programs of each group of mechanisms are a null code combination, i.e. The initial address of the program for every 25 KIN4LU is zero. When the device is turned on, zero code combinations are automatically added to the current address memory block 8. This is done as follows.

When the power supply of the start-up unit 13 is turned on, at its second output, the signal closing the first element occurs. A mentor 14, and. on the first output, forms a short-term pulse. Start the installation (line U). The latter enters the second inputs of the synchronizer U and the counter 12 but: the channel measures, sets them to the initial state, and the first channel code appears on the P bus. Then synchronization is 10 at its liepBOM output (line A ) generates a pulse that does not pass through the 45 closures of the And 14 element, but ensures the formation of the write signal into the counter 5 using the block 6 (communication line N). Since the reading of information from memory block 8 at 50 9T (does not occur, there is zero at its output.; Od, which is recorded in the address counter 5. The report is transmitted first and the change containing the count 5 occurs 55

. same as described. After the command has been processed, the contents of the counter 5 of the address on the bus F are entered

into block 8 of the memory of current addresses by a pulse generated by the synchronizer III at its fifth output (link E). Similarly, there is a conversion at the beginning of the cycle to zero program addresses on the other channels. After the first access to the programs of all channels, the counter 12 returns to its original position, and at its transfer output (communication line 0) a pulse is generated, which arrives at the start block 13.

Under the action of this pulse, the latter generates at its second output a permitting signal arriving at the second input of the first element I 14, which then starts to pass the pulses of the synchronizer 10 to the first control input of the memory block 8 of the current addresses. Due to this, the current address of the program from block 8 is read and rewritten into the counter 5 of the address.

The work program of the device is composed in such a way that the control word written at the zero address of the program contains the code combination of the sensor states needed to start the device and turn on the presence of a signal from the start sensor.

The cycle starts after the arrival of a signal from the start sensor, which, like iace and others, is connected to the input of the switch t. Before the arrival of this signal, the current address of the program is changed, and the HO investigator and the execution of the cycle do not occur. When working out a control word of the first type, the current address of the program does not change until comparator 2 yields a result of the comparison, therefore, the AND commands to turn on and off the mechanisms do not change. If this time exceeds the time allotted for this technological operation of the equipment, which occurs in an emergency situation (sensor or mechanism breakdown), then the device is turned off, the fault is repaired. nosti, and then turn on again.

Figure 2 shows a diagram of the operation of the device when controlling the four channels, while conventionally shown is a different sequence of sequence 1

the strength of the signals, depending on the type of control word and the result of the comparison of signals by a comparator.

In the first channel, in the first step of the program, the command for switching on and off mechanisms is worked out and the transition to the next command is performed, in the second step, the processing of a similar command begins, the address in the address counter 5 does not change and is stored in the current address memory block 8.

In the second canape, the command of the CONDITIONAL transition is satisfied, the condition is not satisfied, the transition to the next command is made. In the third channel, the conditional branch command is also executed, but the condition is fulfilled, in the address counter 5 is entered from the memory block 3, the specified address.

. In the fourth channel, the mechanisms for activating and deactivating the mechanisms are written into the corresponding register of the unit 4.

The address formation control unit 6 (Fig. 3) transmits a pulse arriving along the communication line A from the synchronizer 10 through the element OR the 16th output of the block. This impulse conducts through the communication line N and is perceived by the counter 5 of the address as a signal Writing to block 5. When reading memory block 3, the first type of memory is on its operational output, and the following signal is present on the communication line L, BAN 18 closes and the EQUITY 17 element is prepared for operation. If at the moment of arrival of the pulse from the synchronizer 10 along the line D1, there is 1 along the communication line K (the specified program step has been worked out), then this pulse passes through element I. 15, at the second input of which there is a resolving potential from the equal value 17, From the output of the AND element 15 in this case, an -I signal is output via the communication line M to the address counter 5.

 reading from block 3 of the memory of the word of the second type on its operational output, and therefore on iiiHnot L, signal O, elements UNIFORM 17 and BAN 1) 3 are prepared for operation. If the call arrives on the communication line D by the name 0366. ,

the synchronizer pulse 10 on the communication line K is 1 (the condition of command execution is provided), then this pulse passes through the BANKS .18, OR 16 elements, the communication line N to the control input of the counter-5 address as a signal Record in block 5.

If there is a connection to K (the command execution condition is not met), then a pulse that has been sent along the communication line D passes through the UNIFORM 17, element 15, the communication line M to the input of the counter 5 address as a signal +1.

; The synchronizer 10 (FIG. A) converts a series of pulses coming from generator 9 over a communication line X in the absence of a inhibitory signal and from start-up unit 13 into a sequence of control signals in accordance with a predetermined timing diagram. From the outputs of de5 (entropy 20 and the element of MEMORY 21, which is set to 1 and returned to O, respectively, by signals from the second and fifth outputs of the decoder 20, controlling

0 signals are received in the remaining blocks. devices. The synchronizer is reset to its initial state by the arrival of a pulse along the communication line and which passes

J to the counter 19 and through the element OR 22 - to the element MEMORY 21.

The launch unit 13 (FIG. 5) forms a short-term impulse. The initial installation, which arrives at the communication research institute and to the second input of the synchronizer 10 and the reset input of the counter 12 channel numbers, is set; This pulse occurs: when the device is turned on,

5 when the supply voltage enters the potential input of the single-shot 24, which forms a single, pulse passing through the OR 26 element to the communication line M, with

0 turning on the sensor 25 Initial installation, which generates a pulse. Coming in the same circuit.

The trigger block is also designed to control the passage of the signal that permits reading 5 from the block 8 of the memory of current addresses. Ilpulse initial setup from the output of the element OR 26 is fed to the input R

13

trigger 23, setting it to zero. At the output of the trigger 23 (the second output of the block), a signal O is generated, which closes the first element I 14, as a result of which the synchronizer pulse generated at the first output does not pass through the element 14 at the pen B1 Control input of the memory 8 Read information from block 8 does not occur, a zero code is entered into the counter 5 of the address.

/ This makes it possible to turn to the zero address of the program at the start of the device operation.

After the first access to the programs on all channels of the counter

i 2 channels at the output of the transfer outputs a pulse coming through the communication line tj to the second input of the trigger 23, setting it to 1, from the output of the trigger 23, the signal 1 is fed to the second input of the And t4 element and opens it to pass the pulse from cKHxpoHHsa0366. 14

torus 10 (line A) to the second control input of block B, which is perceived last as a Read command.

5 / The most significant effect from the use of the proposed device can be obtained by controlling complex winding-laying-jamming units, winding-insulating complexes, including transport systems, when there is a need for parallel execution of operations of a single technological process of wrapped stators.

The device can also be used for software-logic control of various discrete-cyclic-action aggregates with constant and variable sequence of operations in cycles, both in electrical engineering and in other industries.

Break by channel by channel yflpa & aeHuff

Compound & Io9p8 Iloka P R. Reading, S / Young $ Recording 6 „f / iOK S Reading Cereal 3 Kind of a weak block 3 output of the convoy Z Record L registers 5. ff / HJK“

/ AZK

four

+ teff / raK f

Record 6 in

one

IS

n

Fig.Z

n

four

sixteen

Sh

dl

P

 to: o;

 "VI

.- - K | - ..,; .: - "

V. p.

 h

g

“M:

FIG. five

Claims (2)

1. DEVICE FOR SOFTWARE EQUIPMENT MANAGEMENT, comprising a comparator, a memory unit, an address counter and an address generation control unit, the first information outputs of the memory unit being connected to the first inputs of the comparator, the output of which is connected to the first input of the address formation control unit, the second input of which is connected with the operational output of the memory unit, and the first and second outputs of the address generation control unit are connected respectively to the counting and control inputs of the address counter, their m · output connected to the first address input of the memory block. The reason is that, in order to improve the performance of the device, it contains a switch, the information input of which is the input of the device, and the output is connected to the second input of the comparator, block of registers, block of elements. OR, first and second AND elements, current address memory block, start-up block, pulse generator, channel number counter and synchronizer, the input of which is connected to the output of the pulse generator9, and from the first to the sixth synchronizer outputs are connected to the first input of the first element And and the third input, the address generation control unit, the control input of the memory unit, the first input of the second AND element, the fourth input of the address formation control unit, the first control input of the memory unit current addresses and to the counting input of the channel number counter, the transfer output of which is connected to the input of the start block, the first output connected to the interconnected reset inputs of the synchronizer and the channel number counter, and the second output to the second input of the first AND element, the output of which is connected to the second the control input of the current address memory unit, the information inputs of which are connected to the output of the address counter, the information input connected via the OR block to the outputs of the current address memory unit and interconnected by the second information output of the memory block and the information input of the register block, and the address inputs of the register block combined with the second address SU .... 1160366 the inputs of the memory block and the address inputs of the switch and the memory block of the current addresses are connected to the information outputs of the channel number counter, the control input of the register block is connected to the output of the second AND element, the second input connected to the operational output of the memory block, and the output of the block registers is the output of the device. 2. The device according to claim 1, with the fact that the address generation control unit contains OR elements, a third AND element, as well as IDENTITY and BAN elements, the first and second inputs of which are connected respectively to each other and connected to the first and second inputs of the block, and the first input of the third AND element is connected to the third input of the FORBID element and the fourth input of the block, the second input to the output of the UNIVERSITY element, and the output to the first output of the block, the third input and the second output of which is connected respectively to the first at the input and output of the OR element, the second input connected to the output of the element is PROHIBITED.