SU1144115A1 - Device for control of dynamic memory - Google Patents

Abstract

A DEVICE FOR DYNAMIC MEMORY MANAGEMENT, containing a regeneration pulse generator, a regeneration address counter, a switch, the output of a regeneration address counter connected to the first information input of the switch, the output of which is connected to the output of the device address, which is , in order to improve the speed of the device, it contains three AND-NOT elements, two AND elements, an OR element, an OR-NOT element, a reversible counter, a sampling signal generator and a regeneration signal generator, the first The input element of the first element IS is NOT connected to the device request input, the second input of the first element AND is NOT connected to the summing input of the reversible counter, the input of which is connected to the output of the regeneration pulse generator, and the output connected to the inputs of the element OR NOT, the output of which is connected to the first input of the first element AND, the second input of which is connected to the output of the first element NAND, and the output is connected to the first input of the element RITli, the second input of which is connected to the output of the second And, the first input of which is connected to the output of the second NAND element, the second information input of the switch is connected to the device address input, the sampling signal generator contains the I element and the delay element, the input of the delay element of the sampling signal generator is connected to the first input of the AND element the sampling signals, the output (of which the output of the delay element of the sampling signal generator is connected to the first control output of the device, the output of the delay element of the signal conditioning generator cleanup connected to the first input of the third AND-NO element whose output is connected to the second control yusche4; device output, and the regenerator signal generator contains two depletion elements and a pulse shaper, and the OR element output is connected to the pulse shaper input element through the first delay element of the regeneration signal generator, the output of which is connected to the second input of the third element NAND, the output of the pulse generator is connected to the second input of the element AND the sampling signal generator, the output of which connected to the second input

Description

The second element is AND, the output of the pulse shaper is connected to the second input of the first element NAND, the output of which is connected to the first input of the element AND shaper

the sampling signals, the output of the pulse generator is connected to the control input of the switch and connected to the counting input of the regeneration address counter.

one

The invention relates to computing and can be used in a computer memory management device made on integrated circuits of semiconductor dynamic memory.

A device for controlling a semiconductor memory is known, comprising a control unit comprising a clock counter, a clock decoder and a control signal generating and output unit, an information regeneration unit comprising a regeneration pulse generator, a regeneration control node and a regeneration address counter, an input-output unit consisting of a clock generator, an address register and a word register, as well as a local control unit, AND, OR elements and pulse generators l

In this device, the regeneration process is allocated to a separate mode of operation and is performed for the entire volume of the addressable memory during the uninterrupted time interval, which requires additional time for regeneration, during which access to the memory is prohibited.

A device is known comprising a regeneration pulse generator, a regeneration address counter, a control unit and a switch, the output of the address counter being connected to the first information input of the switch, the output of which is connected to the output address of the device. In the device, the sequence of regeneration cycles is separated in time so that the next regeneration cycle occurs after a period of time T TP / N so that the drive will have a complete search of the addressable parts of the drive for

time equal to the regeneration period T, where N is the number of cycles of regeneration 2.

A disadvantage of the known device is the synchronous regeneration timing diagram, which leads to conflicts when accessing the memory.

The purpose of the invention is to increase the speed of the device by reducing the average waiting time of the processor when accessing the memory.

The goal is achieved by the fact that a device for managing dynamic memory containing a regeneration pulse generator, a regeneration address counter and a switch, the output of the regeneration address counter connected to the first information input of the switch, the output of which is connected to the output of the device, is entered NOT, two AND elements, OR element, OR-NOT element, reversible counter, sampling signal generator and regeneration signal generator, the first input of the first AND element NOT connected to during the request of the device, the second input of the first element IS-NOT is connected to the summing input of the reversible counter, the input of which is subtracted is connected to the output of the regeneration pulse generator, and the output is connected to the inputs of the second NAND element and connected to the inputs of the SH-NE element whose output is connected to the first input of the first element AND, the second input of which is connected to the output of the first element NAND, and the output is connected to the first input of the OR element, the second input of which is connected to the output of the second AND element, the first input 3 of which is connected to The output of the second element is NOT, the second information input of the switch is connected to the input address of the device, and the sample driver contains an element AND and the delay element input of the delay element of the sample signal generator is connected to the first input of the element And the sample signal generator, the output of which and the output of the delay element the sampling signals are connected to the first control output of the device, the output of the delay element of the sampling signal generator is connected to the first input of the third NAND element, in The output of which is connected to the second control output of the device, and the regeneration signal generator contains two delay elements and a pulse generator, and the output of the OR element is connected to the input of the second delay element through the first delay element of the regeneration signal generator regeneration signal generator whose output is connected to the second input of the third NAND element, pulse generator output is connected to the second input of the element AND is formed The sample signals, the output of which is connected to the second input of the second element AND, the output of the pulse former is connected to the second input of the first NAND element, the output of which is connected to the first input of the element AND the former of the sample signals, the output of the pulse conditioner is connected to the control input the switch and is connected to the counting input of the regeneration address counter. FIG. 1 is a block diagram of a device for managing dynamic memory; in Fig.2 diagram of the signal sampler; Fig. 3 is a diagram of a regeneration signal generator. The device for controlling the dynamic memory contains the first AND-NOT 1 element, the shaper 2 of the sampling signals, the shaper 3 of the response signals, the first AND 4 element of the OR 5, the shaper 6 of the regeneration signals, the reversing counter 7, the second AND-NONE element 8, the second Element And 9, generator 10 pulses regen t5L radio, element OR NOT II, counter 12 addresses regeneration and switch 13. Shaper 2 sampling signals (figure 2) contains the element And 14 and the element 15 delay. Shaper 6 regeneration signals contains the element 16, the delay, the driver 17 pulses and the delay element 18. The proposed device provides the organization of the following regeneration algorithm. The regeneration period is divided into (N t) intervals, with a duration T Tp / (N + m). As in the indicated algorithm, at each interval after the processor accesses the memory in the time interval until the next memory access, the regeneration cycle is completed. However, if during the given time interval the following processor accesses to the memory occur, the backup g-cycles of regeneration are performed, i.e. a buffer is created from the regeneration t-cycles. In this case, if after performing the k backup cycles of regeneration, power is coming through the processor to the memory, then the forced regeneration cycle is required during the time interval. The device has a regeneration buffer counter. When the recovery cycle is performed, its state increases by one, and at the end of the regeneration interval it decreases by one. The accumulated number of backup regeneration cycles does not exceed t, which is ensured by the prohibition of regeneration when the counter assumes the state of go, after which the new regeneration cycle can be executed after the processor has accessed the memory at the end of the current regeneration time interval. If during the duration of several regeneration intervals the processor does not access the memory and the regeneration buffer counter decreases to zero, forced regeneration is performed. Delays in accessing the processor to the memory in this case occur when the request of the processor arrives during the execution of the forced regeneration cycle, since it is impossible to interrupt the regeneration cycle at any time, since this will destroy information. Due to the organization of the regeneration buffer, the probability of coincidence of the moments of forced regeneration and processor access to the memory has a significantly smaller value compared to the methods discussed above. Its value depends on the size of the distribution of the intervals of the following requests, determined by the nature of the program executed on the computer. The device works as follows. In the initial state, the regeneration address counter 12 is in the zero state (resetting this counter to zero occurs cyclically during operation). The reversible counter 7 may be in an arbitrary state before the operation of the device begins. We consider the operation of the device in the example of the use of elements - the K565RUZ memory. From the output of the generator 10 regeneration pulses, pulses with a period of Tr Tp / (N + m) are fed to the second input of the reversible counter for each pulse, its contents are reduced by one. The first input of the NAND 1 element receives a request to access the memory, and the second input receives a signal from the output of the regeneration signal generator 6, which in turn starts the imaging unit 2 of the sampling signals on the second input in the regeneration mode. From the output of the NAND 1 element to the first input of the sampling signal generator 2, the memory enable signal is received, which causes the generation of resolution signals from the row and column (RAS and CAS), respectively. After the memory cycle from the imaging device output 2 sampling signals the first input of the AND 4 element is signaled by the logical unit of completion of the memory access cycle. If the reversible counter 7 is in an intermediate state, i.e. contains on its outputs both zeros and ones, then to the second input of the element I. a logical unit signal will also be received from the output of the NAND 3. element. Thus, immediately after the memory operation is completed, a logical unit signal is sent to the input of the shaper 6 of the regeneration signals and the logical unit starts the shaper 6 to generate a signal the start of the regeneration cycle. This signal arrives at the first input of the switch 13 and switches the switch 13 to read the required regeneration address from the output of the counter 12 of the regeneration address to the drive, to the second input of the AND-NE element 1 and for the time of regeneration, it prohibits the memory to operate in the request (exchange) mode to the second input of the imaging unit 2 of the sampling signals and generates a control signal from the memory in the regeneration mode. At the same time, the signal from the output of the regeneration signal generator is fed to the first input of the reversible counter 7 and to the input of the counter 12 of the regeneration address, where, at the falling front of each subsequent pulse, respectively, it adds one to counter 7 and forms the new address of the array of memory cells of the storage unit that require regeneration, - in the counter 12. With continuous access to the memory, the accumulation of backup regeneration cycles occurs. As soon as the All units appear at the outputs of the reversing counter 7 (the regeneration buffer is full), a logical zero signal appears at the output of the NANDI circuit 8, which prohibits the passage through the AND 4 signals to the input of the regeneration signal generator 6 for processing the next tact of regeneration. In this case, when the next memory request is sent to the first input of the AND-NOT 1 circuit after the current memory cycle is completed, the next regeneration cycle will not occur. In the absence of memory accesses from the signals from the generator 10 regeneration pulses received to the subtractor the input of the reversible counter 7, the state of the counter 7 at some instant decreases to zero, which indicates the necessity of the next forced regeneration cycle. At the output of the OR-NOT 11 circuit, a signal of a logical unit is generated, which is nocrynaej to the second input of the AND 9 element. The first input of the AND 9 element receives a signal from the output of the AND-1 circuit, prohibiting the proc regenerative regeneration cycle, if at a given time already occurs a memory cycle for the next access to it, after which from the output of the AND 4 element on the first input of the OR 5 element, the input of the regeneration signal generator 6 receives a signal and the next natural regeneration cycle is worked out. In the absence of this signal at the first input of the AND 9 element, the signal of the logical unit from the output of the AND 9 element via the second input of the OR element 5 is fed to the input of the regeneration signal generator 6 and the next forced regeneration cycle will be processed at the next address and after its completion in reverse counter 7 at the first input is added to the unit. If there is no further request for working with memory, then for each successive pulse from the generator 10 regeneration pulses arriving at the second input of the reversible counter 7, the counter 7 is zeroed, and at the output of the OR-NB circuit 11 signal of a logical unit that is transmitted through the elements of AND 9 and OR 5 to the input of the regenerator 6 generator, which is followed by the next cycle of forced regeneration at the address formed in the regeneration counter 12. Thus, the invention makes it possible to significantly increase the efficiency of the processor-memory system by reducing the average processor latency when accessing the memory, which provides a significant technical and economic effect.

FIG. 2

FIG 3

Claims (1)

DEVICE FOR MANAGING DYNAMIC MEMORY, comprising a regeneration pulse generator, a regeneration address counter, a switch, the output of the regeneration address counter being connected to the first information input of the switch, the output of which is connected to the output of the device address, which means that, in order to improving the performance of the device, it contains three AND-NOT elements, two AND elements, an OR element, an OR-HE element, a reversible counter, a sampling signal generator and a regeneration signal generator, the first input being of the second AND-NOT element is connected to the device request input, the second input of the first AND-NOT element is connected to the summing input of the reverse counter, the subtraction input of which is connected to the output of the regeneration pulse generator, and the output is connected to the inputs of the second AND-NOT element and connected to the inputs of the element OR-HE, the output of which is connected to the first input of the first AND element, the second input of which is connected to the output of the first AND-NOT element, and the output is connected to the first input of the OR element, the second input of which is connected to the output of the second AND element, the first input of which is connected to the output of the second AND-NOT element, the second information input of the switch is connected to the input of the device address, the sample driver contains the And element and the delay element, the input of the sample delay component of the sample signal is connected to the first input of the sample signal element AND the output of which and the output of the delay element of the sampler are connected to the first control output of the device. The output of the delay element of the sampler is connected to the first input to the third AND-NOT element, the output of which is connected to the second control output of the device, and the regeneration signal generator contains two delay elements and a pulse former, the output of the OR element through the first delay element of the regeneration signal generator is connected to the input of the pulse former, the output of which is connected to the input the second delay element of the regeneration signal generator, the output of which is connected to the second input of the third AND-NOT element, the output of the pulse former is connected to the second input at the AND element of the sampling signal, the output of which is connected to the second input of the second And element, the output of the pulse shaper is connected to the second input of the first AND-NOT element, the output of which is connected to the first input of the And element of the shaper V. Signals' samples, the output of the pulse shaper is connected to the control input of the switch and connected to the counting input of the counter of the regeneration address.