SU1078424A1 - Translator of sequential combination code to parallel binary code - Google Patents

Abstract

CONVERTER OF A SEQUENTIAL COMBINED CODE TO PARALLEL BINARY CODE containing the first, second and third registers, control counter, first element I, first, second and third decoders, counter and pulse generator, the first and second outputs of which are connected respectively to the counter input of the counter and controlling the input of the first decoder, the first, second and third groups of the counter outputs are connected respectively to a group of 5 inputs of the first, second and third decoders, the first outputs of which are connected to, are connected to the inputs of the first element And, the output of which is connected to the inputs of the zero setting of the first, second, third registers and the control counter, characterized in that, in order to expand the functionality due to the possibility of realizing the two-coordinate serial combined code, the switch is entered into it the first and second elements of the comparison and the fourth decoder, the output of which is connected to the control input of the third decoder and the first input of the second element AND, the second input which is connected to the second output of the first decoder, the third output of which and the output of the second element I are respectively the direct and inverse control outputs of the converter, whose information input is connected to the input of the switch, the control inputs of which are connected to the outputs of the third decoder, and the first the second, third outputs of the switch are connected respectively to the synchronization inputs of the first, second and third registers, the group of information inputs of the first register is connected to the group of outputs v The second decoder, the second group of meter outputs is connected to the group (By the second and third register information inputs, the fourth group of meter outputs is connected to the fourth decoder group, the first and second bits of the first register are connected to the inputs of the first comparison element, the output of which is first 4j th bit of the first register, the group of outputs of the second register are the outputs of the first coordinate 4: converter, the output of the control counter is the output of the converter error, the counting 4 input of the control counter is central to the fourth output of the switch, the outputs of the third and fourth bits of the first register are connected to the inputs of the second reference element, the output of which is the third discharge of the first register and the group of outputs of the third register are second outputs. The coordinates of the transducer.

Description

The invention relates to digital computing and can be used to build transducers in coordinate information input panels.

A device is known for converting a serial combined code into a parallel binary code containing AND elements, a counter, decoders, a control counter, a pulse generator, the outputs of which are connected to the counter input and the control counter through the AND element, and the counter outputs are connected to the inputs of the decoder 1,

A disadvantage of the known device is the limited functional capabilities, since it does not produce synchronization pulse systems for the paired device.

The closest in technical essence to the present invention is a device for converting a serial combined code into a parallel binary code containing registers, an element AND, a control counter, decoders, pulse generator, the first and second outputs of which are connected respectively to the counter input of the counter and the control input of the first the decoder, the first, second, third outputs of the counter are connected respectively to the inputs of the first, second third decoders, the first outputs of which are connected to the input first AND gate whose output is connected to the zero setting inputs of the first, second and third registers and control counter. 2

However, such a device has no reliability of conversion, since at its outputs a binary code is formed for only one coordinate, and does not have the ability to generate polling pulses for a source of a sequential code, which makes it difficult to synchronize information signals.

The purpose of the invention is to expand the functionality due to the possibility of realizing the transformation of a two-coordinate sequential combined code.

The goal is achieved in that the converter of the sequential combined code into a parallel binary code containing the first, second and third registers, the control counter, the first element And, the first, second and third decoders, counter and pulse generator, whose first and second outputs are connected respectively, to the counter input of the counter and the control input of the first decoder, first, second, third output group: 1s of the counter are connected respectively to the input groups of the first, second, third decoders, The first outputs of which are connected to the inputs of the first element I, the output of which is connected to the inputs of the zero setting of the first, second, third registers and the control counter, are entered by KoivtMyTaTop, the second element 1 |, the first and second elements of the comparison, and the fourth decoder whose output is connected to the control the input of the third decoder and the first input of the second element And, the second input of which is connected to the second output of the first decoder, the third output of which and the output of the second element And are respectively the direct and inverse control The converter inputs, whose information input is connected to the switch input, whose control inputs are connected to the outputs of the third decoder, and the first, second, and third outputs of the switch are connected to the synchronization inputs of the first, second, and third registers, respectively; the outputs of the second decoder, the second group of outputs of the counter is connected to the groups of information inputs of the second and third registers, the fourth group of outputs the counter is connected to the input group of the fourth decoder, the outputs of the first and second bits of the first register are connected to the inputs of the first comparison element, the output of which is the first discharge of the first register, the group of outputs of the second register are outputs of the first coordinate of the converter, the output of the conversion error is the output of the control counter, the counting input of the control counter is connected to the fourth output of the switch, the outputs of the third and fourth bits of the first register are connected to the inputs of the second el The comparison items whose output together with the third bit output of the first register and the third group of outputs are the second coordinate coordinates. dinaty converter.

The drawing shows the block diagram of the proposed Converter.

The converter includes a generator of 1 pulses, a counter 2, the first, second, third, fourth decoders 3-6, the first element AND switch 8, the first, second, third registers 9-11, the control counter 12, the second element I 13, | first and second elements 14 and 15 of the comparison. Positions 16–46 designate the outputs and inputs of the converter: 47–58 - the output of the converter, 59 - the information input of the converter. Input 16 is the counting input of counter 2, and inputs 17 and 41 are the control inputs of decoder 3 and 5, respectively. Output 42 of the And 7 element is connected to the reset inputs of registers 9-11 and the control counter 12. The switch outputs 43-45 are connected to the synchronization inputs of registers 9-11, and the switch output 46 is connected to the counting input of the control counter 12. The outputs 31 and 47 are the control outputs of the converter, the outputs 48-52 and 53 are respectively the outputs of the first and second coordinates of the converter. The Converter operates as follows. Decoders 3 and 4 work continuously, and decoder 5 only works if there is a signal on drive 4 of decoder 6. Continuous operation, counter 2 causes the entire device to cycle. At the beginning of each cycle of operation, signals appear at the outputs 30, 33, 38 and 41 of the decoders 3-6, and the signal generated at the output 42 of the And 7 element sets the registers 9-11 and the control counter 12 to O. Thereafter, inlet 59 as a result of questioning -. signals at the outputs 31 and 47 of the device. The signals of two pos. the research combined codes by the number of coordinates. The combined code is composed of 2-bit and unitary codes. The code combinations O and 1 2-bit code, in order of increasing, have the form: 1000, 1100, 1110, 1111, 0111, UN, 0001, 0000. The corresponding combinations of the usual binary code have the form: 000, 001, 010, 01 100, 101, 110, 111. With n 2, the bit code has redundant combinations, and their presence is a sign of incorrect reading of information. When n 1, combinations of a 2-bit code are: 10, 11, 01, 00, and the corresponding combinations in the usual binary code look like: 00, 01, 10, 11. The code of the left bit of code combinations is 2-bit This code is fed to input 59 first, for an example implementation of the converter n shown in the drawing, equal to 1. A 2-bit code is converted into a code of lower bits. The high-order code at the output of the converter is obtained when converting a unitary code, the combinations of which are: 10000000, 01000000, 00100000, 00010000, 00001000, 00000100, 00000010, 00000001. The corresponding combinations of the usual binary code are: LLC, 001, 010, 011 , 100, 101, 110, 111. The remaining combinations of the unitary code are redundant and appear only if the information is not read correctly. The left bit code of code combinations of the unitary j code is also input to input 59 first. At the time the pulses are output at the output 38 of the decoder 5 and at the outputs 34 and 35 of the decoder 4, the bit code X arrives at the input 59, its single signals pass through the Vis switch its output 43 affects the synchronization input of register 9, passes to the first two triggers the code from outputs 34 and 35 of the decoder 4. At the time of the pulses at the output 38 of the decoder and the outputs 36 and 37 of the decoder 4, the input 59 receives 2 bits signals also appear output 43 of switch 8, but passing to the third and fourth triggers of register 9 code from outputs 36 and 37 of the decoder 4. At the time of the pulse at output 39 of the decoder 5, input unit 59 receives the unitary code X, its single signal passes through the switch Vis of its output 44 affects the synchronization input of register 10, passes the corresponding code from outputs 21, 22 and 23 of counter 2. At the time of the pulse at output 40 of the decoder 5, the unitary code U arrives at input 59, its single signal passes through the switch Vis of its output 45 on synchronization input register 11, passes into it the corresponding code from the outputs 21, 22 and 23 of counter 2. The unit signals of both unitary codes from the output 46 of the switch 8 arrive at the counting input of the control counter 12. When properly converted, the code at its output takes the value corresponding to 2. The signal at output 58 is used to confirm the accuracy of the information. An output element can be connected to output 58. . An introduction to the proposed device of new nodes and connections leads, as compared with the known device, to an increase in the reliability of code conversion and an increase in functionality.

In the proposed device, an additional code is generated for two coordinates using common nodes. In addition, the ability to form two interrogation pulses simplifies the temporary assignment of input information signals to the device signals, which also increases the reliability of the code conversion.

Claims (1)

'' SERIAL COMBINED CODE CONVERTER In a PARALLEL BINARY CODE, containing the first, second and third registers, a control counter, the first element And, the first, second and third decoders, a counter and a pulse generator, the first and second outputs of which are connected respectively to the counter input of the counter and the control input of the first decoder, the first , the second, third groups of outputs of the counter are connected respectively to the groups of inputs of the first, second and third decoders, the first outputs of which are connected to the inputs of the first AND element, the output of which is connected to the inputs Application of zero first, second and third registers and control counter, characterized in that, in order to increase functionality by allowing the implementation of converting XY combined serial code has been entered in the switch, a second AND gate; the first and second comparison elements and the fourth decoder, the output of which is connected to the control input of the third decoder and the first input of the second element And, the second input of which is connected to the second output of the first decoder, the third output of which and the output of the second element And are respectively the direct and inverse control outputs of the converter , the information input of which is connected to the input of the switch, the control inputs of which are connected to the outputs of the third decoder, and the first, second, third outputs of the switch are are connected respectively to the synchronization inputs of the first, second and third registers, the group of information inputs of the first register is connected to the group of outputs of the second decoder, the second group of outputs of the counter is connected to the groups of information inputs of the second and third registers, the fourth group of outputs of the counter is connected to the group of inputs of the fourth decoder, the outputs of the first and second bits of the first register are connected to the inputs of the first comparison element, the output of which, the output of the first bit of the first register, the group of outputs Odes of the second register are outputs of the first coordinate of the converter, the output of the control counter is the output of the error of the converter, the counting input of the control counter is connected to the fourth output of the switch, the outputs of the third and fourth bits of the first register are connected to the inputs of the second comparison element, the output of which is the output of the third bit of the first register and the group _ of outputs of the third register are outputs of W.-. swarm transducer coordinates. SU., „1078424